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Thu, 5 Sep 2024 16:32:20 +0000 From: Richard Earnshaw To: CC: Richard Earnshaw Subject: [PATCH] arm: avoid indirect sibcalls when IP is live [PR116597] Date: Thu, 5 Sep 2024 17:32:14 +0100 Message-ID: <20240905163214.914479-1-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00027A66:EE_|AS2PR08MB8454:EE_|AMS1EPF0000003F:EE_|DB9PR08MB6524:EE_ X-MS-Office365-Filtering-Correlation-Id: e0e02126-04da-4a02-9179-08dccdc8570a x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info-Original: P0HoiszGH/T27+Hyna4HXj3pume2jr62vhIY+QTX96UgL+6ShbQ5W9sMN5jKjro3P45LHLYOPwRsx517wYyG99XKuoFQFPAmOJtJ3pzjrPIrdtT6ZbQ6chZuvl7p4dsmOvVQ8MXeorMNdsAvcc1Qcz1xPo0R8Bu9HR+XMRweFxhjFty6qHYdB/AcfS4NpYhJ7RIt3rNMV9x7sM7oK6owpYlj+d9AILd87xkuTKECueYD1bC/u4cOBqahebgt9KLHLji+hu5uOVvKRrvxppminSY9guEyhcI3z7jpsNnIaowZ/b+BR/+mEqQTPwaA5E87NAy24KQXugcPPaOQ+fPFoU+7ewjrzUKXAgKqmoACOTvKk2+gp8CDnM1lzaCqmz+FNoXCUIShvoAgaFgo2gC1uNwAVlXYtDOVOkJu6MQY1aUcZBn38By04BHXizwDZu0jzcZuGUjQcJsxllQ8FgnaRG9PzmVSCOgyjM92r9msNhHj+lWLTGn0BH89ZPQjvNiuLhcvpSNghLRI2VOf4K8HpnkpyeO2r7mzDJolEYVpKnHux2t2C9TBFvU2arQ5uiw0llcCQ0M8+o40XBBdoxlP72dhRDv3axfQ1qn6d4fHMDXtHxJo9Q7Aqsi3P1PP0D8+DectFSWOEJv7wg7xFXTzjobrD5TqnjfNBXcw4Dffd0dJxktUjhJMQU0hsxH97W5vfqOtaS89ipo5Lzq8OdeEB06cdc7jR2euk3VOuF0SHovZHisIgwVqp5tV19RQ0Hgr6hAIQyVBgnH/aOtMdFfQbAjwH6nqp1C0xJiNkhqBb67AIY4NjmySB3QSFD1Tnb3wk9NKEmaoeuUMV7FLjkoodLfryBo5RU3m2LZ4u1CnTq8PwB5VPeRxBc2wjY9fLXVZr4skuoe+UPDKUHych0smqfjBNdJHh0dZolvu+LwEKJUZ4JOLZly7OaNoRlzXCLGMRM/iLhgcJu7hYMQSb2ahPzk22JFUZxzy67AdoiW3AJoFs6ye+7YlnlHEfB0yC+GFhth7bVN+da57JoQOzjVC6nUJ20NG17/mrqpcW1pT3/WAfe8zlCwNISUO/Jw7PGk736aS1S0M/G7D/DDFch+lleQ5ogp+khJYCnc0o/ubRGf2zqGOzeauLc3I7bTbK7crgukKm++shnuJ8Dy3PwU8rsuJ4AR44g/Cmt14ct4rIfu1IlOCIkfQAcpZ9aDy0w9FLxXe/qEn6URV9d30z1j7IeNqBdqWdGWQBYH2WrzKdnp+6dhib1CpRzh9/pVuRlmrI49PQOo96Dl4Y18daGeftKyCATsfLJ72lwVuDlRORIqnxiabv1P7SjcOWIpopv2Pihi81hlY+psBy3QaPx7yV1eE4DDNxmi2kLFIGi/WWdyUTGdp3eTBEEoZMYP7HYCz9tHOwWY1lY5Z9SGaTgxAQw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(35042699022); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2024 16:32:31.6606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0e02126-04da-4a02-9179-08dccdc8570a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000003F.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6524 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org On Arm only r0-r3 (the argument registers) and IP are available for use as an address for an indirect sibcall. But if all the argument registers are used and IP is clobbered during the epilogue, or is used to pass closure information, then there is no spare register to hold the address and we must reject the sibcall. arm_function_ok_for_sibcall did try to handle this, but it did this by examining the function declaration. That doesn't work if the function has no prototype, or if the prototype has variadic arguments: we must, instead, look at the list of actuals for the call rather than the list of formals. The old code also worked by laying out all the arguments and then trying to add one more integer argument at the end of the list, but this missed a corner case where a hole had been left in the argument register list due to argument alignment. We fix all of this by now scanning the list of actual values to be passed and then checking if a core register has been assigned to that argument. If it has, then we record which registers were assigned. Once done we then look to see if all the argument registers have been assigned and only block the sibcall if that is the case. This permits us to sibcall: int (*d)(int, ...); int g(void); int i () { return d(g(), 2LL);} because r1 remains free (the 2LL argument is passed in {r2,r3}). gcc/ PR target/116597 * config/arm/arm.cc (arm_function_ok_for_sibcall): Use the list of actuals for the call, not the list of formals. gcc/testsuite/ PR target/116597 * gcc.target/arm/pac-sibcall-2.c: New test. * gcc.target/arm/pac-sibcall-3.c: New test. --- I think the above is all OK, but I'm not especially familiar with handling call expansion. I'll wait until next week before committing this. gcc/config/arm/arm.cc | 38 ++++++++++++++------ gcc/testsuite/gcc.target/arm/pac-sibcall-2.c | 14 ++++++++ gcc/testsuite/gcc.target/arm/pac-sibcall-3.c | 14 ++++++++ 3 files changed, 55 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pac-sibcall-2.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-sibcall-3.c diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 17485447693..de34e9867e6 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -8007,10 +8007,11 @@ arm_function_ok_for_sibcall (tree decl, tree exp) && DECL_WEAK (decl)) return false; - /* We cannot tailcall an indirect call by descriptor if all the call-clobbered - general registers are live (r0-r3 and ip). This can happen when: - - IP contains the static chain, or - - IP is needed for validating the PAC signature. */ + /* Indirect tailcalls need a call-clobbered register to hold the function + address. But we only have r0-r3 and ip in that class. If r0-r3 all hold + function arguments, then we can only use IP. But IP may be needed in the + epilogue (for PAC validation), or for passing the static chain. We have + to disable the tail call if nothing is available. */ if (!decl && ((CALL_EXPR_BY_DESCRIPTOR (exp) && !flag_trampolines) || arm_current_function_pac_enabled_p())) @@ -8022,18 +8023,33 @@ arm_function_ok_for_sibcall (tree decl, tree exp) arm_init_cumulative_args (&cum, fntype, NULL_RTX, NULL_TREE); cum_v = pack_cumulative_args (&cum); - for (tree t = TYPE_ARG_TYPES (fntype); t; t = TREE_CHAIN (t)) + tree arg; + call_expr_arg_iterator iter; + unsigned used_regs = 0; + + /* Layout each actual argument in turn. If it is allocated to + core regs, note which regs have been allocated. */ + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) { - tree type = TREE_VALUE (t); - if (!VOID_TYPE_P (type)) + tree type = TREE_TYPE (arg); + function_arg_info arg_info (type, /*named=*/true); + rtx reg = arm_function_arg (cum_v, arg_info); + if (reg && REG_P (reg) + && REGNO (reg) <= LAST_ARG_REGNUM) { - function_arg_info arg (type, /*named=*/true); - arm_function_arg_advance (cum_v, arg); + /* Avoid any chance of UB here. We don't care if TYPE + is very large since it will use up all the argument regs. */ + unsigned nregs = MIN (ARM_NUM_REGS2 (GET_MODE (reg), type), + LAST_ARG_REGNUM + 1); + used_regs |= ((1 << nregs) - 1) << REGNO (reg); } + arm_function_arg_advance (cum_v, arg_info); } - function_arg_info arg (integer_type_node, /*named=*/true); - if (!arm_function_arg (cum_v, arg)) + /* We've used all the argument regs, and we know IP is live during the + epilogue for some reason, so we can't tailcall. */ + if ((used_regs & ((1 << (LAST_ARG_REGNUM + 1)) - 1)) + == ((1 << (LAST_ARG_REGNUM + 1)) - 1)) return false; } diff --git a/gcc/testsuite/gcc.target/arm/pac-sibcall-2.c b/gcc/testsuite/gcc.target/arm/pac-sibcall-2.c new file mode 100644 index 00000000000..f758e656c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-sibcall-2.c @@ -0,0 +1,14 @@ +/* If all call-clobbered general registers are live (r0-r3, ip), disable + indirect tail-call for a PAC-enabled function. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */ +/* { dg-add-options arm_arch_v8_1m_main_pacbti } */ +/* { dg-additional-options "-mbranch-protection=pac-ret+leaf -O2" } */ + +void fail(void (*f)(int, ...)) +{ + f(1, 2, 3, 4); +} + +/* { dg-final { scan-assembler-not "bx\tip\t@ indirect register sibling call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-sibcall-3.c b/gcc/testsuite/gcc.target/arm/pac-sibcall-3.c new file mode 100644 index 00000000000..1391718d567 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-sibcall-3.c @@ -0,0 +1,14 @@ +/* Although ip is not available, we can make use of a hole in the + argument list for the indirect address (r1 is unused). */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */ +/* { dg-add-options arm_arch_v8_1m_main_pacbti } */ +/* { dg-additional-options "-mbranch-protection=pac-ret+leaf -O2 -std=c99" } */ + +void fail(void (*f)(int, ...)) +{ + f(1, 2LL); +} + +/* { dg-final { scan-assembler "bx\tr1\t@ indirect register sibling call" } } */