diff mbox series

[v2,04/36] arm: [MVE intrinsics] factorize vcvtq

Message ID	20240904132650.2720446-5-christophe.lyon@linaro.org
State	Committed
Commit	e1762af3056f0491d0c2a7d14dcd86d425c4a92e
Delegated to:	Richard Earnshaw
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5A984385841C From: Christophe Lyon <christophe.lyon@linaro.org> To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, ramanara@nvidia.com Cc: Christophe Lyon <christophe.lyon@linaro.org> Subject: [PATCH v2 04/36] arm: [MVE intrinsics] factorize vcvtq Date: Wed, 4 Sep 2024 13:26:18 +0000 Message-Id: <20240904132650.2720446-5-christophe.lyon@linaro.org> In-Reply-To: <20240904132650.2720446-1-christophe.lyon@linaro.org> References: <20240711214305.3193022-1-christophe.lyon@linaro.org> <20240904132650.2720446-1-christophe.lyon@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org
Series	arm: [MVE intrinsics] Re-implement more intrinsics \| [v2,00/36] arm: [MVE intrinsics] Re-implement more intrinsics [v2,01/36] arm: [MVE intrinsics] improve comment for orrq shape [v2,02/36] arm: [MVE intrinsics] remove useless resolve from create shape [v2,03/36] arm: [MVE intrinsics] Cleanup arm-mve-builtins-functions.h [v2,04/36] arm: [MVE intrinsics] factorize vcvtq [v2,05/36] arm: [MVE intrinsics] add vcvt shape [v2,06/36] arm: [MVE intrinsics] rework vcvtq [v2,07/36] arm: [MVE intrinsics] factorize vcvtbq vcvttq [v2,08/36] arm: [MVE intrinsics] add vcvt_f16_f32 and vcvt_f32_f16 shapes [v2,09/36] arm: [MVE intrinsics] rework vcvtbq_f16_f32 vcvttq_f16_f32 vcvtbq_f32_f16 vcvttq_f32_f16 [v2,10/36] arm: [MVE intrinsics] factorize vcvtaq vcvtmq vcvtnq vcvtpq [v2,11/36] arm: [MVE intrinsics] add vcvtx shape [v2,12/36] arm: [MVE intrinsics] rework vcvtaq vcvtmq vcvtnq vcvtpq [v2,13/36] arm: [MVE intrinsics] rework vbicq [v2,14/36] arm: [MVE intrinsics] factorize vorn [v2,15/36] arm: [MVE intrinsics] rework vorn [v2,16/36] arm: [MVE intrinsics] rework vctp [v2,17/36] arm: [MVE intrinsics] factorize vddup vidup [v2,18/36] arm: [MVE intrinsics] add viddup shape [v2,19/36] arm: [MVE intrinsics] rework vddup vidup [v2,20/36] arm: [MVE intrinsics] update v[id]dup tests [v2,21/36] arm: [MVE intrinsics] remove v[id]dup expanders [v2,22/36] arm: [MVE intrinsics] fix checks of immediate arguments [v2,23/36] arm: [MVE intrinsics] factorize vdwdup viwdup [v2,24/36] arm: [MVE intrinsics] add vidwdup shape [v2,25/36] arm: [MVE intrinsics] rework vdwdup viwdup [v2,26/36] arm: [MVE intrinsics] update v[id]wdup tests [v2,27/36] arm: [MVE intrinsics] remove useless v[id]wdup expanders [v2,28/36] arm: [MVE intrinsics] add vshlc shape [v2,29/36] arm: [MVE intrinsics] rework vshlcq [v2,30/36] arm: [MVE intrinsics] remove vshlcq useless expanders [v2,31/36] arm: [MVE intrinsics] add vadc_vsbc shape [v2,32/36] arm: [MVE intrinsics] factorize vadc vadci vsbc vsbci [v2,33/36] arm: [MVE intrinsics] rework vadciq [v2,34/36] arm: [MVE intrinsics] rework vadcq [v2,35/36] arm: [MVE intrinsics] rework vsbcq vsbciq [v2,36/36] arm: [MVE intrinsics] use long_type_suffix / half_type_suffix helpers

Commit Message

Christophe Lyon Sept. 4, 2024, 1:26 p.m. UTC

  Factorize vcvtq so that they use parameterized names.

2024-07-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (mve_insn): Add VCVTQ_FROM_F_S,
	VCVTQ_FROM_F_U, VCVTQ_M_FROM_F_S, VCVTQ_M_FROM_F_U,
	VCVTQ_M_N_FROM_F_S, VCVTQ_M_N_FROM_F_U, VCVTQ_M_N_TO_F_S,
	VCVTQ_M_N_TO_F_U, VCVTQ_M_TO_F_S, VCVTQ_M_TO_F_U,
	VCVTQ_N_FROM_F_S, VCVTQ_N_FROM_F_U, VCVTQ_N_TO_F_S,
	VCVTQ_N_TO_F_U, VCVTQ_TO_F_S, VCVTQ_TO_F_U.
	* config/arm/mve.md (mve_vcvtq_to_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_to_f_<supf><mode>.
	(mve_vcvtq_from_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_from_f_<supf><mode>.
	(mve_vcvtq_n_to_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_n_to_f_<supf><mode>.
	(mve_vcvtq_n_from_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_n_from_f_<supf><mode>.
	(mve_vcvtq_m_to_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_to_f_<supf><mode>.
	(mve_vcvtq_m_n_from_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_n_from_f_<supf><mode>.
	(mve_vcvtq_m_from_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_from_f_<supf><mode>.
	(mve_vcvtq_m_n_to_f_<supf><mode>): Rename into
	@mve_<mve_insn>q_m_n_to_f_<supf><mode>.
---
 gcc/config/arm/iterators.md |  8 +++++
 gcc/config/arm/mve.md       | 64 ++++++++++++++++++-------------------
 2 files changed, 40 insertions(+), 32 deletions(-)

Comments

Richard Earnshaw (lists) Oct. 14, 2024, 4:48 p.m. UTC | #1

On 04/09/2024 14:26, Christophe Lyon wrote:
> Factorize vcvtq so that they use parameterized names.
> 
> 2024-07-11  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	gcc/
> 	* config/arm/iterators.md (mve_insn): Add VCVTQ_FROM_F_S,
> 	VCVTQ_FROM_F_U, VCVTQ_M_FROM_F_S, VCVTQ_M_FROM_F_U,
> 	VCVTQ_M_N_FROM_F_S, VCVTQ_M_N_FROM_F_U, VCVTQ_M_N_TO_F_S,
> 	VCVTQ_M_N_TO_F_U, VCVTQ_M_TO_F_S, VCVTQ_M_TO_F_U,
> 	VCVTQ_N_FROM_F_S, VCVTQ_N_FROM_F_U, VCVTQ_N_TO_F_S,
> 	VCVTQ_N_TO_F_U, VCVTQ_TO_F_S, VCVTQ_TO_F_U.
> 	* config/arm/mve.md (mve_vcvtq_to_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_to_f_<supf><mode>.
> 	(mve_vcvtq_from_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_from_f_<supf><mode>.
> 	(mve_vcvtq_n_to_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_n_to_f_<supf><mode>.
> 	(mve_vcvtq_n_from_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_n_from_f_<supf><mode>.
> 	(mve_vcvtq_m_to_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_m_to_f_<supf><mode>.
> 	(mve_vcvtq_m_n_from_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_m_n_from_f_<supf><mode>.
> 	(mve_vcvtq_m_from_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_m_from_f_<supf><mode>.
> 	(mve_vcvtq_m_n_to_f_<supf><mode>): Rename into
> 	@mve_<mve_insn>q_m_n_to_f_<supf><mode>.

OK.

R.

> ---
>  gcc/config/arm/iterators.md |  8 +++++
>  gcc/config/arm/mve.md       | 64 ++++++++++++++++++-------------------
>  2 files changed, 40 insertions(+), 32 deletions(-)
> 
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index b9ff01cb104..bf800625fac 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -964,6 +964,14 @@ (define_int_attr mve_insn [
>  		 (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla")
>  		 (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul")
>  		 (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate")
> +		 (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt")
> +		 (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt")
> +		 (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt")
> +		 (VCVTQ_M_N_TO_F_S "vcvt") (VCVTQ_M_N_TO_F_U "vcvt")
> +		 (VCVTQ_M_TO_F_S "vcvt") (VCVTQ_M_TO_F_U "vcvt")
> +		 (VCVTQ_N_FROM_F_S "vcvt") (VCVTQ_N_FROM_F_U "vcvt")
> +		 (VCVTQ_N_TO_F_S "vcvt") (VCVTQ_N_TO_F_U "vcvt")
> +		 (VCVTQ_TO_F_S "vcvt") (VCVTQ_TO_F_U "vcvt")
>  		 (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup")
>  		 (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup")
>  		 (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 706a45c7d66..95c615c1534 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -248,17 +248,17 @@ (define_insn "mve_vcvtbq_f32_f16v4sf"
>  ])
>  
>  ;;
> -;; [vcvtq_to_f_s, vcvtq_to_f_u])
> +;; [vcvtq_to_f_s, vcvtq_to_f_u]
>  ;;
> -(define_insn "mve_vcvtq_to_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_to_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_0 0 "s_register_operand" "=w")
>  	(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
>  	 VCVTQ_TO_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
> +  "<mve_insn>.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>  ])
>  
> @@ -278,17 +278,17 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>"
>  ])
>  
>  ;;
> -;; [vcvtq_from_f_s, vcvtq_from_f_u])
> +;; [vcvtq_from_f_s, vcvtq_from_f_u]
>  ;;
> -(define_insn "mve_vcvtq_from_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_from_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_5 0 "s_register_operand" "=w")
>  	(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
>  	 VCVTQ_FROM_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
> +  "<mve_insn>.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>  ])
>  
> @@ -581,9 +581,9 @@ (define_insn "@mve_<mve_insn>q_n_f<mode>"
>  ])
>  
>  ;;
> -;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
> +;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]
>  ;;
> -(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_n_to_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_0 0 "s_register_operand" "=w")
>  	(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
> @@ -591,8 +591,8 @@ (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
>  	 VCVTQ_N_TO_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
> +  "<mve_insn>.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>  ])
>  
> @@ -679,9 +679,9 @@ (define_insn "mve_vshrq_n_u<mode>_imm"
>  ])
>  
>  ;;
> -;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
> +;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]
>  ;;
> -(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_n_from_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_5 0 "s_register_operand" "=w")
>  	(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
> @@ -689,8 +689,8 @@ (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
>  	 VCVTQ_N_FROM_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
> +  "<mve_insn>.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>  ])
>  
> @@ -1672,9 +1672,9 @@ (define_insn "mve_vcvtaq_m_<supf><mode>"
>    (set_attr "length""8")])
>  
>  ;;
> -;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
> +;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]
>  ;;
> -(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_to_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_0 0 "s_register_operand" "=w")
>  	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
> @@ -1683,8 +1683,8 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
>  	 VCVTQ_M_TO_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
> +  "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>    (set_attr "length""8")])
>  
> @@ -2651,9 +2651,9 @@ (define_insn "mve_vcvtnq_m_<supf><mode>"
>     (set_attr "length""8")])
>  
>  ;;
> -;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
> +;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]
>  ;;
> -(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_n_from_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_5 0 "s_register_operand" "=w")
>  	(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
> @@ -2663,8 +2663,8 @@ (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
>  	 VCVTQ_M_N_FROM_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
> +  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>     (set_attr "length""8")])
>  
> @@ -2686,9 +2686,9 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
>     (set_attr "length""8")])
>  
>  ;;
> -;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
> +;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]
>  ;;
> -(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_from_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_5 0 "s_register_operand" "=w")
>  	(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
> @@ -2697,8 +2697,8 @@ (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
>  	 VCVTQ_M_FROM_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
> +  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>    (set_attr "length""8")])
>  
> @@ -2757,9 +2757,9 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
>    (set_attr "length" "8")])
>  
>  ;;
> -;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
> +;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]
>  ;;
> -(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_n_to_f_<supf><mode>"
>    [
>     (set (match_operand:MVE_0 0 "s_register_operand" "=w")
>  	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
> @@ -2769,8 +2769,8 @@ (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
>  	 VCVTQ_M_N_TO_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
> - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
> +  "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
> + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
>    (set_attr "type" "mve_move")
>     (set_attr "length""8")])
>

diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index b9ff01cb104..bf800625fac 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -964,6 +964,14 @@  (define_int_attr mve_insn [
 		 (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla")
 		 (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul")
 		 (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate")
+		 (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt")
+		 (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt")
+		 (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt")
+		 (VCVTQ_M_N_TO_F_S "vcvt") (VCVTQ_M_N_TO_F_U "vcvt")
+		 (VCVTQ_M_TO_F_S "vcvt") (VCVTQ_M_TO_F_U "vcvt")
+		 (VCVTQ_N_FROM_F_S "vcvt") (VCVTQ_N_FROM_F_U "vcvt")
+		 (VCVTQ_N_TO_F_S "vcvt") (VCVTQ_N_TO_F_U "vcvt")
+		 (VCVTQ_TO_F_S "vcvt") (VCVTQ_TO_F_U "vcvt")
 		 (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup")
 		 (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup")
 		 (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 706a45c7d66..95c615c1534 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -248,17 +248,17 @@  (define_insn "mve_vcvtbq_f32_f16v4sf"
 ])
 
 ;;
-;; [vcvtq_to_f_s, vcvtq_to_f_u])
+;; [vcvtq_to_f_s, vcvtq_to_f_u]
 ;;
-(define_insn "mve_vcvtq_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_to_f_<supf><mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 	 VCVTQ_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
+  "<mve_insn>.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
   (set_attr "type" "mve_move")
 ])
 
@@ -278,17 +278,17 @@  (define_insn "@mve_<mve_insn>q_<supf><mode>"
 ])
 
 ;;
-;; [vcvtq_from_f_s, vcvtq_from_f_u])
+;; [vcvtq_from_f_s, vcvtq_from_f_u]
 ;;
-(define_insn "mve_vcvtq_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_from_f_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
 	 VCVTQ_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
+  "<mve_insn>.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
   (set_attr "type" "mve_move")
 ])
 
@@ -581,9 +581,9 @@  (define_insn "@mve_<mve_insn>q_n_f<mode>"
 ])
 
 ;;
-;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
+;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]
 ;;
-(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_to_f_<supf><mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
@@ -591,8 +591,8 @@  (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
 	 VCVTQ_N_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
+  "<mve_insn>.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
   (set_attr "type" "mve_move")
 ])
 
@@ -679,9 +679,9 @@  (define_insn "mve_vshrq_n_u<mode>_imm"
 ])
 
 ;;
-;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
+;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]
 ;;
-(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_from_f_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
@@ -689,8 +689,8 @@  (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
 	 VCVTQ_N_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
+  "<mve_insn>.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
   (set_attr "type" "mve_move")
 ])
 
@@ -1672,9 +1672,9 @@  (define_insn "mve_vcvtaq_m_<supf><mode>"
   (set_attr "length""8")])
 
 ;;
-;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
+;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]
 ;;
-(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_to_f_<supf><mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
@@ -1683,8 +1683,8 @@  (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
 	 VCVTQ_M_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
+  "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
   (set_attr "type" "mve_move")
   (set_attr "length""8")])
 
@@ -2651,9 +2651,9 @@  (define_insn "mve_vcvtnq_m_<supf><mode>"
    (set_attr "length""8")])
 
 ;;
-;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
+;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]
 ;;
-(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_from_f_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
@@ -2663,8 +2663,8 @@  (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
 	 VCVTQ_M_N_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
   (set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -2686,9 +2686,9 @@  (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
    (set_attr "length""8")])
 
 ;;
-;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
+;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]
 ;;
-(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_from_f_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
@@ -2697,8 +2697,8 @@  (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
 	 VCVTQ_M_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
   (set_attr "type" "mve_move")
   (set_attr "length""8")])
 
@@ -2757,9 +2757,9 @@  (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   (set_attr "length" "8")])
 
 ;;
-;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
+;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]
 ;;
-(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_to_f_<supf><mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
@@ -2769,8 +2769,8 @@  (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
 	 VCVTQ_M_N_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
+  "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
   (set_attr "type" "mve_move")
    (set_attr "length""8")])