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Wed, 04 Sep 2024 06:27:35 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5dfa0580692sm2308062eaf.46.2024.09.04.06.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2024 06:27:35 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, ramanara@nvidia.com Cc: Christophe Lyon Subject: [PATCH v2 17/36] arm: [MVE intrinsics] factorize vddup vidup Date: Wed, 4 Sep 2024 13:26:31 +0000 Message-Id: <20240904132650.2720446-18-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240904132650.2720446-1-christophe.lyon@linaro.org> References: <20240711214305.3193022-1-christophe.lyon@linaro.org> <20240904132650.2720446-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Factorize vddup and vidup so that they use the same parameterized names. This patch updates only the (define_insn "@mve_q_u_insn") patterns and does not bother with the (define_expand "mve_vidupq_n_u") ones, because a subsequent patch avoids using them. 2024-08-21 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add VIDUPQ, VDDUPQ, VIDUPQ_M, VDDUPQ_M. (viddupq_op): New. (viddupq_m_op): New. (VIDDUPQ): New. (VIDDUPQ_M): New. * config/arm/mve.md (mve_vddupq_u_insn) (mve_vidupq_u_insn): Merge into ... (mve_q_u_insn): ... this. (mve_vddupq_m_wb_u_insn, mve_vidupq_m_wb_u_insn): Merge into ... (mve_q_m_wb_u_insn): ... this. --- gcc/config/arm/iterators.md | 7 +++++ gcc/config/arm/mve.md | 58 +++++++++---------------------------- 2 files changed, 20 insertions(+), 45 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 3a1825ebab2..c0299117f26 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1007,6 +1007,8 @@ (define_int_attr mve_insn [ (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub") (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub") (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub") + (VIDUPQ "vidup") (VDDUPQ "vddup") + (VIDUPQ_M "vidup") (VDDUPQ_M "vddup") (VMAXAQ_M_S "vmaxa") (VMAXAQ_S "vmaxa") (VMAXAVQ_P_S "vmaxav") @@ -1340,6 +1342,9 @@ (define_int_attr mve_mnemo [ (VRNDXQ_F "vrintx") (VRNDXQ_M_F "vrintx") ]) +(define_int_attr viddupq_op [ (VIDUPQ "plus") (VDDUPQ "minus")]) +(define_int_attr viddupq_m_op [ (VIDUPQ_M "plus") (VDDUPQ_M "minus")]) + ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows ;; a stack pointer operand. The minus operation is a candidate for an rsub ;; and hence only plus is supported. @@ -2961,6 +2966,8 @@ (define_int_iterator VCVTxQ_M_F16_F32 [VCVTBQ_M_F16_F32 VCVTTQ_M_F16_F32]) (define_int_iterator VCVTxQ_M_F32_F16 [VCVTBQ_M_F32_F16 VCVTTQ_M_F32_F16]) (define_int_iterator VCVTxQ [VCVTAQ_S VCVTAQ_U VCVTMQ_S VCVTMQ_U VCVTNQ_S VCVTNQ_U VCVTPQ_S VCVTPQ_U]) (define_int_iterator VCVTxQ_M [VCVTAQ_M_S VCVTAQ_M_U VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S VCVTNQ_M_U VCVTPQ_M_S VCVTPQ_M_U]) +(define_int_iterator VIDDUPQ [VIDUPQ VDDUPQ]) +(define_int_iterator VIDDUPQ_M [VIDUPQ_M VDDUPQ_M]) (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32 DLSTP64]) (define_int_iterator LETP [LETP8 LETP16 LETP32 diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 62cffebd6ed..36117303fd6 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -5105,18 +5105,18 @@ (define_expand "mve_vidupq_n_u" }) ;; -;; [vidupq_u_insn]) +;; [vddupq_u_insn, vidupq_u_insn] ;; -(define_insn "mve_vidupq_u_insn" +(define_insn "@mve_q_u_insn" [(set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] - VIDUPQ)) + VIDDUPQ)) (set (match_operand:SI 1 "s_register_operand" "=Te") - (plus:SI (match_dup 2) - (match_operand:SI 4 "immediate_operand" "i")))] + (:SI (match_dup 2) + (match_operand:SI 4 "immediate_operand" "i")))] "TARGET_HAVE_MVE" - "vidup.u%#\t%q0, %1, %3") + ".u%#\t%q0, %1, %3") ;; ;; [vidupq_m_n_u]) @@ -5139,21 +5139,21 @@ (define_expand "mve_vidupq_m_n_u" }) ;; -;; [vidupq_m_wb_u_insn]) +;; [vddupq_m_wb_u_insn, vidupq_m_wb_u_insn] ;; -(define_insn "mve_vidupq_m_wb_u_insn" +(define_insn "@mve_q_m_wb_u_insn" [(set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 3 "s_register_operand" "2") (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") (match_operand: 5 "vpr_register_operand" "Up")] - VIDUPQ_M)) + VIDDUPQ_M)) (set (match_operand:SI 2 "s_register_operand" "=Te") - (plus:SI (match_dup 3) - (match_operand:SI 6 "immediate_operand" "i")))] + (:SI (match_dup 3) + (match_operand:SI 6 "immediate_operand" "i")))] "TARGET_HAVE_MVE" - "vpst\;\tvidupt.u%#\t%q0, %2, %4" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vidupq_u_insn")) + "vpst\;t.u%#\t%q0, %2, %4" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_u_insn")) (set_attr "length""8")]) ;; @@ -5173,20 +5173,6 @@ (define_expand "mve_vddupq_n_u" DONE; }) -;; -;; [vddupq_u_insn]) -;; -(define_insn "mve_vddupq_u_insn" - [(set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") - (match_operand:SI 3 "immediate_operand" "i")] - VDDUPQ)) - (set (match_operand:SI 1 "s_register_operand" "=Te") - (minus:SI (match_dup 2) - (match_operand:SI 4 "immediate_operand" "i")))] - "TARGET_HAVE_MVE" - "vddup.u%#\t%q0, %1, %3") - ;; ;; [vddupq_m_n_u]) ;; @@ -5207,24 +5193,6 @@ (define_expand "mve_vddupq_m_n_u" DONE; }) -;; -;; [vddupq_m_wb_u_insn]) -;; -(define_insn "mve_vddupq_m_wb_u_insn" - [(set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:SI 3 "s_register_operand" "2") - (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") - (match_operand: 5 "vpr_register_operand" "Up")] - VDDUPQ_M)) - (set (match_operand:SI 2 "s_register_operand" "=Te") - (minus:SI (match_dup 3) - (match_operand:SI 6 "immediate_operand" "i")))] - "TARGET_HAVE_MVE" - "vpst\;vddupt.u%#\t%q0, %2, %4" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vddupq_u_insn")) - (set_attr "length""8")]) - ;; ;; [vdwdupq_n_u]) ;;