diff mbox series

[1/3] RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test

Message ID 20240807062714.2989672-1-christoph.muellner@vrull.eu
State Committed
Commit 8e6bc6dd2bb476fa97586b477bc98c670a3fcaf0
Delegated to: Jeff Law
Headers
Series [1/3] RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test |

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Commit Message

Christoph Müllner Aug. 7, 2024, 6:27 a.m. UTC 
  Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
test case that provoked an ICE when loading DFmode registers via two
SImode register loads followed by a SI->DF[63:32] move from XTheadFmv.
Since Zfa is affected in the same way as XTheadFmv, even if both
have slightly different instructions, let's add a test for Zfa as well
and give the tests proper names.

Let's also add a test into the test files that counts the SI->DF moves
from XTheadFmv/Zfa.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmemidx-medany.c: Move to...
	* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
	* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 ...any.c => xtheadfmemidx-xtheadfmv-medany.c} |  5 ++-
 .../riscv/xtheadfmemidx-zfa-medany.c          | 39 +++++++++++++++++++
 2 files changed, 42 insertions(+), 2 deletions(-)
 rename gcc/testsuite/gcc.target/riscv/{xtheadfmemidx-medany.c => xtheadfmemidx-xtheadfmv-medany.c} (71%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c

Comments

Jeff Law Aug. 7, 2024, 2:48 p.m. UTC | #1 
On 8/7/24 12:27 AM, Christoph Müllner wrote:
> Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
> test case that provoked an ICE when loading DFmode registers via two
> SImode register loads followed by a SI->DF[63:32] move from XTheadFmv.
> Since Zfa is affected in the same way as XTheadFmv, even if both
> have slightly different instructions, let's add a test for Zfa as well
> and give the tests proper names.
> 
> Let's also add a test into the test files that counts the SI->DF moves
> from XTheadFmv/Zfa.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/xtheadfmemidx-medany.c: Move to...
> 	* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
> 	* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.
OK
jeff
Christoph Müllner Aug. 8, 2024, 2:34 p.m. UTC | #2 
On Wed, Aug 7, 2024 at 4:48 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 8/7/24 12:27 AM, Christoph Müllner wrote:
> > Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
> > test case that provoked an ICE when loading DFmode registers via two
> > SImode register loads followed by a SI->DF[63:32] move from XTheadFmv.
> > Since Zfa is affected in the same way as XTheadFmv, even if both
> > have slightly different instructions, let's add a test for Zfa as well
> > and give the tests proper names.
> >
> > Let's also add a test into the test files that counts the SI->DF moves
> > from XTheadFmv/Zfa.
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/xtheadfmemidx-medany.c: Move to...
> >       * gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
> >       * gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.
> OK
> jeff

OK to backport the three patches of this series on GCC 14 (which is
also affected by PR116131)?
Jeff Law Aug. 8, 2024, 2:37 p.m. UTC | #3 
On 8/8/24 8:34 AM, Christoph Müllner wrote:
> On Wed, Aug 7, 2024 at 4:48 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 8/7/24 12:27 AM, Christoph Müllner wrote:
>>> Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
>>> test case that provoked an ICE when loading DFmode registers via two
>>> SImode register loads followed by a SI->DF[63:32] move from XTheadFmv.
>>> Since Zfa is affected in the same way as XTheadFmv, even if both
>>> have slightly different instructions, let's add a test for Zfa as well
>>> and give the tests proper names.
>>>
>>> Let's also add a test into the test files that counts the SI->DF moves
>>> from XTheadFmv/Zfa.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>>        * gcc.target/riscv/xtheadfmemidx-medany.c: Move to...
>>>        * gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
>>>        * gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.
>> OK
>> jeff
> 
> OK to backport the three patches of this series on GCC 14 (which is
> also affected by PR116131)?
Of course.
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
similarity index 71%
rename from gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c
rename to gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 0c8060d06329..7c70b7758246 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz"} } */
-/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx -mabi=ilp32d -mcmodel=medany -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx -mabi=ilp32d -mcmodel=medany" } */
 
 typedef union {
   double v;
@@ -36,3 +36,4 @@  double foo (int i, int j)
 }
 
 /* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
new file mode 100644
index 000000000000..4215eab11951
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -0,0 +1,39 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc_zfa_xtheadfmemidx_xtheadmemidx -mabi=ilp32d -mcmodel=medany" } */
+
+typedef union {
+  double v;
+  unsigned w;
+} my_t;
+
+double z;
+
+double foo (int i, int j)
+{
+
+  if (j)
+    {
+      switch (i)
+	{
+	case 0:
+	  return 1;
+	case 1:
+	  return 0;
+	case 2:
+	  return 3.0;
+	}
+    }
+
+  if (i == 1)
+    {
+      my_t u;
+      u.v = z;
+      u.w = 1;
+      z = u.v;
+    }
+  return z;
+}
+
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */