[3/3] RISC-V: Fix typos in code
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Commit Message
This fixes typos in function names and executed code.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc (num_occurences_in_str): Rename...
(num_occurrences_in_str): here.
(riscv_process_target_attr): Update num_occurences_in_str callsite.
* config/riscv/riscv-v.cc (emit_vec_widden_cvt_x_f): widden -> widen.
(emit_vec_widen_cvt_x_f): Ditto.
(emit_vec_widden_cvt_f_f): Ditto.
(emit_vec_widen_cvt_f_f): Ditto.
(emit_vec_rounding_to_integer): Update *widden* callsites.
* config/riscv/riscv-vector-builtins.cc (expand_builtin): Update
required_ext_to_isa_name callsite and fix xtheadvector typo.
* config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): Rename...
(required_ext_to_isa_name): here.
* config/riscv/riscv_th_vector.h: Fix endif label.
* config/riscv/vector-crypto.md: boardcast_scalar -> broadcast_scalar.
* config/riscv/vector.md: Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Relying on precommit for full testing.
---
gcc/config/riscv/riscv-target-attr.cc | 4 +-
gcc/config/riscv/riscv-v.cc | 10 +--
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
gcc/config/riscv/riscv-vector-builtins.h | 4 +-
gcc/config/riscv/riscv_th_vector.h | 2 +-
gcc/config/riscv/vector-crypto.md | 8 +--
gcc/config/riscv/vector.md | 74 +++++++++++------------
7 files changed, 52 insertions(+), 52 deletions(-)
--
2.34.1
Comments
On Tue, Aug 6, 2024 at 12:29 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> This fixes typos in function names and executed code.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc (num_occurences_in_str): Rename...
> (num_occurrences_in_str): here.
> (riscv_process_target_attr): Update num_occurences_in_str callsite.
> * config/riscv/riscv-v.cc (emit_vec_widden_cvt_x_f): widden -> widen.
> (emit_vec_widen_cvt_x_f): Ditto.
> (emit_vec_widden_cvt_f_f): Ditto.
> (emit_vec_widen_cvt_f_f): Ditto.
> (emit_vec_rounding_to_integer): Update *widden* callsites.
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Update
> required_ext_to_isa_name callsite and fix xtheadvector typo.
> * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): Rename...
> (required_ext_to_isa_name): here.
> * config/riscv/riscv_th_vector.h: Fix endif label.
> * config/riscv/vector-crypto.md: boardcast_scalar -> broadcast_scalar.
> * config/riscv/vector.md: Ditto.
>
> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
> ---
> Relying on precommit for full testing.
> ---
> gcc/config/riscv/riscv-target-attr.cc | 4 +-
> gcc/config/riscv/riscv-v.cc | 10 +--
> gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
> gcc/config/riscv/riscv-vector-builtins.h | 4 +-
> gcc/config/riscv/riscv_th_vector.h | 2 +-
> gcc/config/riscv/vector-crypto.md | 8 +--
> gcc/config/riscv/vector.md | 74 +++++++++++------------
> 7 files changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-target-attr.cc b/gcc/config/riscv/riscv-target-attr.cc
> index 1645a669217..bf14ade5ce0 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -290,7 +290,7 @@ riscv_process_one_target_attr (char *arg_str,
> NULL-terminated string STR. */
>
> static unsigned int
> -num_occurences_in_str (char c, char *str)
> +num_occurrences_in_str (char c, char *str)
This could also be "backported" to aarch64.cc.
> {
> unsigned int res = 0;
> while (*str != '\0')
> @@ -347,7 +347,7 @@ riscv_process_target_attr (tree args, location_t loc)
>
> /* Used to catch empty spaces between semi-colons i.e.
> attribute ((target ("attr1;;attr2"))). */
> - unsigned int num_semicolons = num_occurences_in_str (';', str_to_check);
> + unsigned int num_semicolons = num_occurrences_in_str (';', str_to_check);
>
> /* Handle multiple target attributes separated by ';'. */
> char *token = strtok_r (str_to_check, ";", &str_to_check);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 90a156221af..0db5c7591ef 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4599,7 +4599,7 @@ emit_vec_narrow_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
> }
>
> static void
> -emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
> +emit_vec_widen_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
> machine_mode vec_mode)
> {
> rtx ops[] = {op_dest, op_src};
> @@ -4609,7 +4609,7 @@ emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
> }
>
> static void
> -emit_vec_widden_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
> +emit_vec_widen_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
> machine_mode vec_mode)
> {
> rtx ops[] = {op_dest, op_src};
> @@ -4835,7 +4835,7 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1, insn_type type,
> else if (maybe_eq (vec_fp_size, vec_int_size * 2)) /* DF => SI. */
> emit_vec_narrow_cvt_x_f (op_0, op_1, type, vec_fp_mode);
> else if (maybe_eq (vec_fp_size * 2, vec_int_size)) /* SF => DI, HF => SI. */
> - emit_vec_widden_cvt_x_f (op_0, op_1, type, vec_int_mode);
> + emit_vec_widen_cvt_x_f (op_0, op_1, type, vec_int_mode);
> else if (maybe_eq (vec_fp_size * 4, vec_int_size)) /* HF => DI. */
> {
> gcc_assert (vec_bridge_mode != E_VOIDmode);
> @@ -4843,9 +4843,9 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1, insn_type type,
> rtx op_sf = gen_reg_rtx (vec_bridge_mode);
>
> /* Step-1: HF => SF, no rounding here. */
> - emit_vec_widden_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
> + emit_vec_widen_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
> /* Step-2: SF => DI. */
> - emit_vec_widden_cvt_x_f (op_0, op_sf, type, vec_int_mode);
> + emit_vec_widen_cvt_x_f (op_0, op_sf, type, vec_int_mode);
> }
> else
> gcc_unreachable ();
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 3d73514ffb0..9f707efa533 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4765,7 +4765,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
> error_at (EXPR_LOCATION (exp),
> "built-in function %qE requires the %qs ISA extension",
> exp,
> - reqired_ext_to_isa_name (rfn.required));
> + required_ext_to_isa_name (rfn.required));
> return target;
> }
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
> index b4445fa6d5d..f092dbfa3be 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.h
> +++ b/gcc/config/riscv/riscv-vector-builtins.h
> @@ -130,7 +130,7 @@ enum required_ext
> /* Please update below to isa_name func when add or remove enum type(s). */
> };
>
> -static inline const char * reqired_ext_to_isa_name (enum required_ext required)
> +static inline const char * required_ext_to_isa_name (enum required_ext required)
> {
> switch (required)
> {
> @@ -155,7 +155,7 @@ static inline const char * reqired_ext_to_isa_name (enum required_ext required)
> case ZVKSH_EXT:
> return "zvksh";
> case XTHEADVECTOR_EXT:
> - return "xthreadvector";
> + return "xtheadvector";
> case ZVFBFMIN_EXT:
> return "zvfbfmin";
> case ZVFBFWMA_EXT:
> diff --git a/gcc/config/riscv/riscv_th_vector.h b/gcc/config/riscv/riscv_th_vector.h
> index b6b6738bdda..78ef853d79b 100644
> --- a/gcc/config/riscv/riscv_th_vector.h
> +++ b/gcc/config/riscv/riscv_th_vector.h
> @@ -46,4 +46,4 @@ extern "C" {
> }
> #endif // __cplusplus
> #endif // __riscv_xtheadvector
> -#endif // __RISCV_TH_ECTOR_H
> +#endif // __RISCV_TH_VECTOR_H
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 17432b15815..db372bef645 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -168,9 +168,9 @@
> /* vl */operands[5],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_vandn<mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -409,9 +409,9 @@
> /* vl */operands[5],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_vclmul<h><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 203a41fbde3..aad34b3aa24 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1793,7 +1793,7 @@
> ;; constraint alternative 2 match vse.v.
> ;; constraint alternative 3 match vmv.v.v.
>
> -;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
> +;; If operand 3 is a const_vector, then it is left to pred_broadcast patterns.
> (define_expand "@pred_mov<mode>"
> [(set (match_operand:V_VLS 0 "nonimmediate_operand")
> (if_then_else:V_VLS
> @@ -1971,9 +1971,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::simm5_p (operands[3]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
> - operands[2], boardcast_scalar, operands[4], operands[5],
> + operands[2], broadcast_scalar, operands[4], operands[5],
> operands[6], operands[7]));
> },
> (riscv_vector::avl_type) INTVAL (operands[7])))
> @@ -2756,9 +2756,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -2832,9 +2832,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -2908,9 +2908,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::neg_simm5_p (operands[4]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
> - operands[2], boardcast_scalar, operands[3], operands[5],
> + operands[2], broadcast_scalar, operands[3], operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -3026,9 +3026,9 @@
> /* vl */operands[5],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -3201,9 +3201,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::simm5_p (operands[3]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
> - operands[2], boardcast_scalar, operands[4], operands[5],
> + operands[2], broadcast_scalar, operands[4], operands[5],
> operands[6], operands[7]));
> },
> (riscv_vector::avl_type) INTVAL (operands[7])))
> @@ -3285,9 +3285,9 @@
> /* vl */operands[5],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
> - operands[2], boardcast_scalar, operands[4], operands[5],
> + operands[2], broadcast_scalar, operands[4], operands[5],
> operands[6], operands[7]));
> },
> (riscv_vector::avl_type) INTVAL (operands[7])))
> @@ -3448,9 +3448,9 @@
> /* vl */operands[4],
> <MODE>mode,
> riscv_vector::simm5_p (operands[2]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4], operands[5]));
> + broadcast_scalar, operands[3], operands[4], operands[5]));
> },
> (riscv_vector::avl_type) INTVAL (operands[5])))
> DONE;
> @@ -3520,9 +3520,9 @@
> /* vl */operands[4],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4], operands[5]));
> + broadcast_scalar, operands[3], operands[4], operands[5]));
> },
> (riscv_vector::avl_type) INTVAL (operands[5])))
> DONE;
> @@ -3669,9 +3669,9 @@
> /* vl */operands[3],
> <MODE>mode,
> riscv_vector::simm5_p (operands[2]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4]));
> + broadcast_scalar, operands[3], operands[4]));
> },
> (riscv_vector::avl_type) INTVAL (operands[4])))
> DONE;
> @@ -3738,9 +3738,9 @@
> /* vl */operands[3],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4]));
> + broadcast_scalar, operands[3], operands[4]));
> },
> (riscv_vector::avl_type) INTVAL (operands[4])))
> DONE;
> @@ -4300,9 +4300,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -4376,9 +4376,9 @@
> /* vl */operands[5],
> <MODE>mode,
> riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -4522,9 +4522,9 @@
> /* vl */operands[5],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
> - operands[2], operands[3], boardcast_scalar, operands[5],
> + operands[2], operands[3], broadcast_scalar, operands[5],
> operands[6], operands[7], operands[8], operands[9]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -4907,15 +4907,15 @@
> <MODE>mode,
> riscv_vector::has_vi_variant_p (code, operands[5]),
> code == LT || code == LTU ?
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
> - operands[2], operands[3], operands[4], boardcast_scalar,
> + operands[2], operands[3], operands[4], broadcast_scalar,
> operands[6], operands[7], operands[8]));
> }
> :
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
> - operands[2], operands[3], operands[4], boardcast_scalar,
> + operands[2], operands[3], operands[4], broadcast_scalar,
> operands[6], operands[7], operands[8]));
> },
> (riscv_vector::avl_type) INTVAL (operands[8])))
> @@ -5407,9 +5407,9 @@
> /* vl */operands[6],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4], operands[5],
> + broadcast_scalar, operands[3], operands[4], operands[5],
> operands[6], operands[7], operands[8], operands[9]));
> },
> (riscv_vector::avl_type) INTVAL (operands[9])))
> @@ -5705,9 +5705,9 @@
> /* vl */operands[6],
> <MODE>mode,
> false,
> - [] (rtx *operands, rtx boardcast_scalar) {
> + [] (rtx *operands, rtx broadcast_scalar) {
> emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
> - boardcast_scalar, operands[3], operands[4], operands[5],
> + broadcast_scalar, operands[3], operands[4], operands[5],
> operands[6], operands[7], operands[8], operands[9]));
> },
> (riscv_vector::avl_type) INTVAL (operands[9])))
> --
> 2.34.1
>
On 8/5/24 4:29 PM, Patrick O'Neill wrote:
> This fixes typos in function names and executed code.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc (num_occurences_in_str): Rename...
> (num_occurrences_in_str): here.
> (riscv_process_target_attr): Update num_occurences_in_str callsite.
> * config/riscv/riscv-v.cc (emit_vec_widden_cvt_x_f): widden -> widen.
> (emit_vec_widen_cvt_x_f): Ditto.
> (emit_vec_widden_cvt_f_f): Ditto.
> (emit_vec_widen_cvt_f_f): Ditto.
> (emit_vec_rounding_to_integer): Update *widden* callsites.
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Update
> required_ext_to_isa_name callsite and fix xtheadvector typo.
> * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): Rename...
> (required_ext_to_isa_name): here.
> * config/riscv/riscv_th_vector.h: Fix endif label.
> * config/riscv/vector-crypto.md: boardcast_scalar -> broadcast_scalar.
> * config/riscv/vector.md: Ditto.
These are OK as well and would probably be considered OK under the
obvious rule too.
jeff
On 8/5/24 20:20, Jeff Law wrote:
>
>
> On 8/5/24 4:29 PM, Patrick O'Neill wrote:
>> This fixes typos in function names and executed code.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-target-attr.cc (num_occurences_in_str):
>> Rename...
>> (num_occurrences_in_str): here.
>> (riscv_process_target_attr): Update num_occurences_in_str callsite.
>> * config/riscv/riscv-v.cc (emit_vec_widden_cvt_x_f): widden ->
>> widen.
>> (emit_vec_widen_cvt_x_f): Ditto.
>> (emit_vec_widden_cvt_f_f): Ditto.
>> (emit_vec_widen_cvt_f_f): Ditto.
>> (emit_vec_rounding_to_integer): Update *widden* callsites.
>> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Update
>> required_ext_to_isa_name callsite and fix xtheadvector typo.
>> * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name):
>> Rename...
>> (required_ext_to_isa_name): here.
>> * config/riscv/riscv_th_vector.h: Fix endif label.
>> * config/riscv/vector-crypto.md: boardcast_scalar ->
>> broadcast_scalar.
>> * config/riscv/vector.md: Ditto.
> These are OK as well and would probably be considered OK under the
> obvious rule too.
>
> jeff
>
Committed.
Patrick
@@ -290,7 +290,7 @@ riscv_process_one_target_attr (char *arg_str,
NULL-terminated string STR. */
static unsigned int
-num_occurences_in_str (char c, char *str)
+num_occurrences_in_str (char c, char *str)
{
unsigned int res = 0;
while (*str != '\0')
@@ -347,7 +347,7 @@ riscv_process_target_attr (tree args, location_t loc)
/* Used to catch empty spaces between semi-colons i.e.
attribute ((target ("attr1;;attr2"))). */
- unsigned int num_semicolons = num_occurences_in_str (';', str_to_check);
+ unsigned int num_semicolons = num_occurrences_in_str (';', str_to_check);
/* Handle multiple target attributes separated by ';'. */
char *token = strtok_r (str_to_check, ";", &str_to_check);
@@ -4599,7 +4599,7 @@ emit_vec_narrow_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
}
static void
-emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
+emit_vec_widen_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
machine_mode vec_mode)
{
rtx ops[] = {op_dest, op_src};
@@ -4609,7 +4609,7 @@ emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
}
static void
-emit_vec_widden_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
+emit_vec_widen_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
machine_mode vec_mode)
{
rtx ops[] = {op_dest, op_src};
@@ -4835,7 +4835,7 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1, insn_type type,
else if (maybe_eq (vec_fp_size, vec_int_size * 2)) /* DF => SI. */
emit_vec_narrow_cvt_x_f (op_0, op_1, type, vec_fp_mode);
else if (maybe_eq (vec_fp_size * 2, vec_int_size)) /* SF => DI, HF => SI. */
- emit_vec_widden_cvt_x_f (op_0, op_1, type, vec_int_mode);
+ emit_vec_widen_cvt_x_f (op_0, op_1, type, vec_int_mode);
else if (maybe_eq (vec_fp_size * 4, vec_int_size)) /* HF => DI. */
{
gcc_assert (vec_bridge_mode != E_VOIDmode);
@@ -4843,9 +4843,9 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1, insn_type type,
rtx op_sf = gen_reg_rtx (vec_bridge_mode);
/* Step-1: HF => SF, no rounding here. */
- emit_vec_widden_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
+ emit_vec_widen_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
/* Step-2: SF => DI. */
- emit_vec_widden_cvt_x_f (op_0, op_sf, type, vec_int_mode);
+ emit_vec_widen_cvt_x_f (op_0, op_sf, type, vec_int_mode);
}
else
gcc_unreachable ();
@@ -4765,7 +4765,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
error_at (EXPR_LOCATION (exp),
"built-in function %qE requires the %qs ISA extension",
exp,
- reqired_ext_to_isa_name (rfn.required));
+ required_ext_to_isa_name (rfn.required));
return target;
}
@@ -130,7 +130,7 @@ enum required_ext
/* Please update below to isa_name func when add or remove enum type(s). */
};
-static inline const char * reqired_ext_to_isa_name (enum required_ext required)
+static inline const char * required_ext_to_isa_name (enum required_ext required)
{
switch (required)
{
@@ -155,7 +155,7 @@ static inline const char * reqired_ext_to_isa_name (enum required_ext required)
case ZVKSH_EXT:
return "zvksh";
case XTHEADVECTOR_EXT:
- return "xthreadvector";
+ return "xtheadvector";
case ZVFBFMIN_EXT:
return "zvfbfmin";
case ZVFBFWMA_EXT:
@@ -46,4 +46,4 @@ extern "C" {
}
#endif // __cplusplus
#endif // __riscv_xtheadvector
-#endif // __RISCV_TH_ECTOR_H
+#endif // __RISCV_TH_VECTOR_H
@@ -168,9 +168,9 @@
/* vl */operands[5],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_vandn<mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -409,9 +409,9 @@
/* vl */operands[5],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_vclmul<h><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -1793,7 +1793,7 @@
;; constraint alternative 2 match vse.v.
;; constraint alternative 3 match vmv.v.v.
-;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
+;; If operand 3 is a const_vector, then it is left to pred_broadcast patterns.
(define_expand "@pred_mov<mode>"
[(set (match_operand:V_VLS 0 "nonimmediate_operand")
(if_then_else:V_VLS
@@ -1971,9 +1971,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::simm5_p (operands[3]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
- operands[2], boardcast_scalar, operands[4], operands[5],
+ operands[2], broadcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
},
(riscv_vector::avl_type) INTVAL (operands[7])))
@@ -2756,9 +2756,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -2832,9 +2832,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -2908,9 +2908,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::neg_simm5_p (operands[4]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
- operands[2], boardcast_scalar, operands[3], operands[5],
+ operands[2], broadcast_scalar, operands[3], operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -3026,9 +3026,9 @@
/* vl */operands[5],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -3201,9 +3201,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::simm5_p (operands[3]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
- operands[2], boardcast_scalar, operands[4], operands[5],
+ operands[2], broadcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
},
(riscv_vector::avl_type) INTVAL (operands[7])))
@@ -3285,9 +3285,9 @@
/* vl */operands[5],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
- operands[2], boardcast_scalar, operands[4], operands[5],
+ operands[2], broadcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
},
(riscv_vector::avl_type) INTVAL (operands[7])))
@@ -3448,9 +3448,9 @@
/* vl */operands[4],
<MODE>mode,
riscv_vector::simm5_p (operands[2]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4], operands[5]));
+ broadcast_scalar, operands[3], operands[4], operands[5]));
},
(riscv_vector::avl_type) INTVAL (operands[5])))
DONE;
@@ -3520,9 +3520,9 @@
/* vl */operands[4],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4], operands[5]));
+ broadcast_scalar, operands[3], operands[4], operands[5]));
},
(riscv_vector::avl_type) INTVAL (operands[5])))
DONE;
@@ -3669,9 +3669,9 @@
/* vl */operands[3],
<MODE>mode,
riscv_vector::simm5_p (operands[2]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4]));
+ broadcast_scalar, operands[3], operands[4]));
},
(riscv_vector::avl_type) INTVAL (operands[4])))
DONE;
@@ -3738,9 +3738,9 @@
/* vl */operands[3],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4]));
+ broadcast_scalar, operands[3], operands[4]));
},
(riscv_vector::avl_type) INTVAL (operands[4])))
DONE;
@@ -4300,9 +4300,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -4376,9 +4376,9 @@
/* vl */operands[5],
<MODE>mode,
riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -4522,9 +4522,9 @@
/* vl */operands[5],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
- operands[2], operands[3], boardcast_scalar, operands[5],
+ operands[2], operands[3], broadcast_scalar, operands[5],
operands[6], operands[7], operands[8], operands[9]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -4907,15 +4907,15 @@
<MODE>mode,
riscv_vector::has_vi_variant_p (code, operands[5]),
code == LT || code == LTU ?
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
- operands[2], operands[3], operands[4], boardcast_scalar,
+ operands[2], operands[3], operands[4], broadcast_scalar,
operands[6], operands[7], operands[8]));
}
:
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
- operands[2], operands[3], operands[4], boardcast_scalar,
+ operands[2], operands[3], operands[4], broadcast_scalar,
operands[6], operands[7], operands[8]));
},
(riscv_vector::avl_type) INTVAL (operands[8])))
@@ -5407,9 +5407,9 @@
/* vl */operands[6],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4], operands[5],
+ broadcast_scalar, operands[3], operands[4], operands[5],
operands[6], operands[7], operands[8], operands[9]));
},
(riscv_vector::avl_type) INTVAL (operands[9])))
@@ -5705,9 +5705,9 @@
/* vl */operands[6],
<MODE>mode,
false,
- [] (rtx *operands, rtx boardcast_scalar) {
+ [] (rtx *operands, rtx broadcast_scalar) {
emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
- boardcast_scalar, operands[3], operands[4], operands[5],
+ broadcast_scalar, operands[3], operands[4], operands[5],
operands[6], operands[7], operands[8], operands[9]));
},
(riscv_vector::avl_type) INTVAL (operands[9])))