diff mbox series

[v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change

Message ID 20240805080111.26478-1-pan2.li@intel.com
State Committed
Commit 1b5c57e53e7ee4087e10f51fcf74968d950d3d83
Delegated to: Jeff Law
Headers
Series [v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change |

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Commit Message

Li, Pan2 Aug. 5, 2024, 8:01 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Due to recent middle-end change, update the .SAT_TRUNC expand dump
check from 2 to 4.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Adjust
	asm check times from 2 to 4.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

钟居哲 Aug. 5, 2024, 10:20 a.m. UTC | #1 
lgtm



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2024-08-05 16:01
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
From: Pan Li <pan2.li@intel.com>
 
Due to recent middle-end change, update the .SAT_TRUNC expand dump
check from 2 to 4.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Adjust
asm check times from 2 to 4.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c       | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 7f047f3f6a2..ae3e44cd57e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -16,4 +16,4 @@
*/
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
-- 
2.43.0
Jeff Law Aug. 5, 2024, 1:53 p.m. UTC | #2 
On 8/5/24 2:01 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> Due to recent middle-end change, update the .SAT_TRUNC expand dump
> check from 2 to 4.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Adjust
> 	asm check times from 2 to 4.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 7f047f3f6a2..ae3e44cd57e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -16,4 +16,4 @@ 
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */