diff mbox series

RISC-V: c implies zca, and conditionally zcf & zcd

Message ID 20240710101202.26798-1-gaofei@eswincomputing.com
State Committed
Delegated to: Jeff Law
Headers
Series RISC-V: c implies zca, and conditionally zcf & zcd |

Checks

Context Check Description
rivoscibot/toolchain-ci-rivos-lint success Lint passed
rivoscibot/toolchain-ci-rivos-apply-patch success Patch applied
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gcv-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv64gcv-lp64d-multilib success Build passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Build passed
rivoscibot/toolchain-ci-rivos-build--newlib-rv32imc_zba_zbb_zbc_zbs-ilp32d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gc-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv32gc_zba_zbb_zbc_zbs-ilp32d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv64gc_zba_zbb_zbc_zbs-lp64d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-test fail Testing failed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm warning Patch is already merged

Commit Message

Fei Gao July 10, 2024, 10:12 a.m. UTC 
  According to Zc-1.0.4-3.pdf from
https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
The rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd

Signed-off-by: Fei Gao <gaofei@eswincomputing.com>
gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc:
	c implies zca, and conditionally zcf & zcd.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-15.c: adapt TC.
	* gcc.target/riscv/attribute-16.c: likewise.
	* gcc.target/riscv/attribute-17.c: likewise.
	* gcc.target/riscv/attribute-18.c: likewise.
	* gcc.target/riscv/pr110696.c: likewise.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise.
	* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
	* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
	* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
	* gcc.target/riscv/arch-39.c: New test.
	* gcc.target/riscv/arch-40.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc              | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/arch-39.c             |  7 +++++++
 gcc/testsuite/gcc.target/riscv/arch-40.c             |  7 +++++++
 gcc/testsuite/gcc.target/riscv/attribute-15.c        |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-16.c        |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-17.c        |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-18.c        |  2 +-
 gcc/testsuite/gcc.target/riscv/pr110696.c            |  2 +-
 .../riscv/rvv/base/abi-callee-saved-1-zcmp.c         |  2 +-
 .../riscv/rvv/base/abi-callee-saved-2-zcmp.c         |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c |  8 ++++----
 12 files changed, 39 insertions(+), 13 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c

Comments

Jeff Law July 10, 2024, 4:13 p.m. UTC | #1 
On 7/10/24 4:12 AM, Fei Gao wrote:
> According to Zc-1.0.4-3.pdf from
> https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
> The rule is that:
> - C always implies Zca
> - C+F implies Zcf (RV32 only)
> - C+D implies Zcd
> 
> Signed-off-by: Fei Gao <gaofei@eswincomputing.com>
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc:
> 	c implies zca, and conditionally zcf & zcd.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/attribute-15.c: adapt TC.
> 	* gcc.target/riscv/attribute-16.c: likewise.
> 	* gcc.target/riscv/attribute-17.c: likewise.
> 	* gcc.target/riscv/attribute-18.c: likewise.
> 	* gcc.target/riscv/pr110696.c: likewise.
> 	* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise.
> 	* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
> 	* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
> 	* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
> 	* gcc.target/riscv/arch-39.c: New test.
> 	* gcc.target/riscv/arch-40.c: New test.
OK.

jeff
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index b9bda3e110a..8622f7f3c79 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -82,6 +82,18 @@  static const riscv_implied_info_t riscv_implied_info[] =
   {"a", "zaamo"},
   {"a", "zalrsc"},
 
+  {"c", "zca"},
+  {"c", "zcf",
+   [] (const riscv_subset_list *subset_list) -> bool
+   {
+     return subset_list->xlen () == 32 && subset_list->lookup ("f");
+   }},
+  {"c", "zcd",
+   [] (const riscv_subset_list *subset_list) -> bool
+   {
+     return subset_list->lookup ("d");
+   }},
+
   {"zabha", "zaamo"},
 
   {"zdinx", "zfinx"},
diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c b/gcc/testsuite/gcc.target/riscv/arch-39.c
new file mode 100644
index 00000000000..beeb81e44c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-39.c
@@ -0,0 +1,7 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c b/gcc/testsuite/gcc.target/riscv/arch-40.c
new file mode 100644
index 00000000000..eaefaf1d0d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-40.c
@@ -0,0 +1,7 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
index a2e394b6489..ac6caaecd4f 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
@@ -3,4 +3,4 @@ 
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
index d2b18160cb5..539e426ca97 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
@@ -3,4 +3,4 @@ 
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
index fc2f488a3ac..30928cb5b68 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
@@ -3,4 +3,4 @@ 
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
index eefd602103d..9f7199f331a 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
@@ -1,4 +1,4 @@ 
 /* { dg-do compile } */
 /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
 int foo() {}
-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
index 08682a047e0..aae2afc6b28 100644
--- a/gcc/testsuite/gcc.target/riscv/pr110696.c
+++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
@@ -4,4 +4,4 @@  int foo()
 {
 }
 
-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
index dedcef9b353..b6b708f1a58 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
+/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
index 14fb2c400a4..5f8f96f86a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
+/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
index faeb406498d..300d87324c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
@@ -54,5 +54,5 @@  test_3 (int *a, int *b, int *out, unsigned count)
     out[i] = a[i] + b[i];
 }
 
-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
index 38815ef5bd0..da7a44ba08a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
@@ -107,7 +107,7 @@  test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
     out[i] = a[i] + b[i];
 }
 
-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */