diff mbox series

[2/2] LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.

Message ID 20240702032200.26875-2-chenglulu@loongson.cn
State New
Headers
Series [1/2] LoongArch: Fix explicit-relocs-{extreme-, }tls-desc.c tests. |

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Commit Message

Lulu Cheng July 2, 2024, 3:22 a.m. UTC 
  The following two FAIL items have been fixed:

FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movcf2fr\\t\\\\\$f[0-9]+,\\\\\$fcc
FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movfr2gr\\\\.s\\t\\\\\$r4

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_insn_cost):
	New function.
	(TARGET_INSN_COST): New macro.
---
 gcc/config/loongarch/loongarch.cc | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Comments

Xi Ruoyao July 2, 2024, 3:50 a.m. UTC | #1 
On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
> +static int
> +loongarch_insn_cost (rtx_insn *insn, bool speed)
> +{
> +  rtx x = PATTERN (insn);
> +  int cost = pattern_cost (x, speed);
> +
> +  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
> +  if (TARGET_uARCH_LA464 && GET_CODE (x) == SET
> +      && GET_MODE (XEXP (x, 0)) == FCCmode)
> +    {
> +      rtx dest, src;
> +      dest = XEXP (x, 0);
> +      src = XEXP (x, 1);
> +
> +      if (REG_P (dest) && REG_P (src))
> +	{
> +	  if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
> +	    cost = COSTS_N_INSNS (7);

cost = loongarch_cost->movcf2gr;

> +	  else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
> +	    cost = COSTS_N_INSNS (15);

cost = loongarch_cost->movgr2cf;

Then we don't need to check TARGET_uARCH_LA464.

> +	}
> +    }
> +  return cost;
> +}
Lulu Cheng July 2, 2024, 4:04 a.m. UTC | #2 
在 2024/7/2 上午11:50, Xi Ruoyao 写道:
> On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
>> +static int
>> +loongarch_insn_cost (rtx_insn *insn, bool speed)
>> +{
>> +  rtx x = PATTERN (insn);
>> +  int cost = pattern_cost (x, speed);
>> +
>> +  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
>> +  if (TARGET_uARCH_LA464 && GET_CODE (x) == SET
>> +      && GET_MODE (XEXP (x, 0)) == FCCmode)
>> +    {
>> +      rtx dest, src;
>> +      dest = XEXP (x, 0);
>> +      src = XEXP (x, 1);
>> +
>> +      if (REG_P (dest) && REG_P (src))
>> +	{
>> +	  if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
>> +	    cost = COSTS_N_INSNS (7);
> cost = loongarch_cost->movcf2gr;
>
>> +	  else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
>> +	    cost = COSTS_N_INSNS (15);
> cost = loongarch_cost->movgr2cf;
>
> Then we don't need to check TARGET_uARCH_LA464.

Ok! I'll merge it after the revisions.

Thanks.

>
>> +	}
>> +    }
>> +  return cost;
>> +}
Lulu Cheng July 2, 2024, 8:14 a.m. UTC | #3 
Modified and pushed to r15-1765.

在 2024/7/2 上午11:50, Xi Ruoyao 写道:
> On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
>> +static int
>> +loongarch_insn_cost (rtx_insn *insn, bool speed)
>> +{
>> +  rtx x = PATTERN (insn);
>> +  int cost = pattern_cost (x, speed);
>> +
>> +  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
>> +  if (TARGET_uARCH_LA464 && GET_CODE (x) == SET
>> +      && GET_MODE (XEXP (x, 0)) == FCCmode)
>> +    {
>> +      rtx dest, src;
>> +      dest = XEXP (x, 0);
>> +      src = XEXP (x, 1);
>> +
>> +      if (REG_P (dest) && REG_P (src))
>> +	{
>> +	  if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
>> +	    cost = COSTS_N_INSNS (7);
> cost = loongarch_cost->movcf2gr;
>
>> +	  else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
>> +	    cost = COSTS_N_INSNS (15);
> cost = loongarch_cost->movgr2cf;
>
> Then we don't need to check TARGET_uARCH_LA464.
>
>> +	}
>> +    }
>> +  return cost;
>> +}
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 0fb547e00f4..cf21c365605 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4372,6 +4372,34 @@  loongarch_address_cost (rtx addr, machine_mode mode,
   return loongarch_address_insns (addr, mode, false);
 }
 
+/* Implement TARGET_INSN_COST.  */
+
+static int
+loongarch_insn_cost (rtx_insn *insn, bool speed)
+{
+  rtx x = PATTERN (insn);
+  int cost = pattern_cost (x, speed);
+
+  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
+  if (TARGET_uARCH_LA464 && GET_CODE (x) == SET
+      && GET_MODE (XEXP (x, 0)) == FCCmode)
+    {
+      rtx dest, src;
+      dest = XEXP (x, 0);
+      src = XEXP (x, 1);
+
+      if (REG_P (dest) && REG_P (src))
+	{
+	  if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
+	    cost = COSTS_N_INSNS (7);
+	  else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
+	    cost = COSTS_N_INSNS (15);
+	}
+    }
+  return cost;
+}
+
+
 /* Return one word of double-word value OP, taking into account the fixed
    endianness of certain registers.  HIGH_P is true to select the high part,
    false to select the low part.  */
@@ -11105,6 +11133,8 @@  loongarch_asm_code_end (void)
 #define TARGET_RTX_COSTS loongarch_rtx_costs
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST loongarch_address_cost
+#undef TARGET_INSN_COST
+#define TARGET_INSN_COST loongarch_insn_cost
 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
   loongarch_builtin_vectorization_cost