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Fri, 26 Apr 2024 10:37:19 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64: Use cinc for small constants instead of just add [PR112304] Date: Fri, 26 Apr 2024 10:37:02 -0700 Message-ID: <20240426173702.3006187-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3sAEIPaSiZjQNG4tRm5xAz01jWxkKPJG X-Proofpoint-GUID: 3sAEIPaSiZjQNG4tRm5xAz01jWxkKPJG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-26_14,2024-04-26_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=707 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404260119 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org On many cores, the mov instruction is "free" so the sequence: cmp w0, #0 cset w0, ne add w0, w0, 42 is more expensive than just: cmp w0, #0 mov w1, #42 cinc w0, w1, ne The reason why we get the add case is that the pattern csinc2_insn only accepts registers for the predicate and we so we don't get an cinc without that. The small change to the predicate of using general_operand instead allows the combine to match and then the mov is generated with the register allocator checks the constraints. Built and tested on aarch64-linux-gnu with no regressions. PR target/112304 gcc/ChangeLog: * config/aarch64/aarch64.md (*csinc2_insn): Change the predicate of the 1st operand to general_operand. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cinc-2.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.md | 2 +- gcc/testsuite/gcc.target/aarch64/cinc-2.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/cinc-2.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a6051ebfc5a..046a249475d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4549,7 +4549,7 @@ (define_insn "aarch64_" (define_insn "*csinc2_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_operand 2 "aarch64_comparison_operation" "") - (match_operand:GPI 1 "register_operand" "r")))] + (match_operand:GPI 1 "general_operand" "r")))] "" "cinc\\t%0, %1, %m2" [(set_attr "type" "csel")] diff --git a/gcc/testsuite/gcc.target/aarch64/cinc-2.c b/gcc/testsuite/gcc.target/aarch64/cinc-2.c new file mode 100644 index 00000000000..dc68dfed40f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cinc-2.c @@ -0,0 +1,11 @@ +/* { dg-options "-O2" } */ +/* PR target/112304 */ + +int f(int a) +{ + return (a!=0)+42; +} + +/* This function should produce a cinc with a mov instead of a cset with an add. */ +/* { dg-final { scan-assembler-not "cset\t" } } */ +/* { dg-final { scan-assembler "cinc\t" } } */