From patchwork Tue Apr 9 07:04:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 88220 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D3933858289 for ; Tue, 9 Apr 2024 07:05:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 959B13858289 for ; Tue, 9 Apr 2024 07:04:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 959B13858289 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 959B13858289 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712646296; cv=none; b=V/UlwyMg6ByQLH5ZB53zQN9ozmFtZ/uqi+BIwW2v+fhRsKyBoCOkYfqLzWf2saAyPvXXtsb5qlRsynMqlQQRng9Vz2i8XsTqVzkmy1XkIuH/3tXyHBltEMD+tZx/Ea5Uu3rkDiTTmdnZEAVlIaJahSVMLyqIrgcEHq+YsK9/+1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712646296; c=relaxed/simple; bh=AUl6dAlHI0qMq6xnEZUjABISBgcsjp3E0jhCbQ00vW8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=L78Wp6DL7ozFDbf8P326s6xiTDYU5xvuq6TW8wg8rZ84itKHJW2nBvedtu86nB7raAvisdseuYvXGjN6OC1J0ZLWePhtcYwcuc3krl4rtXL7n6ZF2bboY3xFB2Se2wfsfzqPpjNAS7rkNinn+pRPciQTTNCqpwJp+EhhZp6a+BM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712646295; x=1744182295; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=AUl6dAlHI0qMq6xnEZUjABISBgcsjp3E0jhCbQ00vW8=; b=L/KvlbVN47yPyKW7nKPnluMtALnF/MrhdZuIuee1O/JRilE1rBwls8Kl fLJKoKmZEB6Po28do1C3LzBCzxX4QaZ00ocb0NAuNabcXQ3mEjzb/9Mfo KK6oM3mOY6xAOJNWrzDWSheZRFBnU6mvoH4K8KEclr98H78rR6yPXy3Tx iksXhXuUNOkM18dPnwMIfP/j35AcFU2WNhwI7gqT4imjfWuP9eeuTeh33 ZnoL260Ih8LIhG/AHyQ4baGSGt0Dh6RTKio+z6hn+qdM2/TS4PjUaoXNR Ii3T2G1iE6Y5N6yMEv7Kps2fiCyie22iqmZnujCv4Guj0djzL8XQlPJs3 w==; X-CSE-ConnectionGUID: sc4rO8+JSQCqm0R+FVHhJQ== X-CSE-MsgGUID: os5pbNIlT/OmD8b9OERbSw== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="7793846" X-IronPort-AV: E=Sophos;i="6.07,188,1708416000"; d="scan'208";a="7793846" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 00:04:54 -0700 X-CSE-ConnectionGUID: EdDvrlmGTjqmDWX+MlzQDw== X-CSE-MsgGUID: /foCXjoFSZORcZh/zTczxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,188,1708416000"; d="scan'208";a="20161270" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa006.fm.intel.com with ESMTP; 09 Apr 2024 00:04:52 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1AC451005666; Tue, 9 Apr 2024 15:04:51 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com Subject: [PATCH] Prohibit SHA/KEYLOCKER usage of EGPR when APX enabled Date: Tue, 9 Apr 2024 15:04:51 +0800 Message-Id: <20240409070451.150551-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org The latest APX spec announced removal of SHA/KEYLOCKER evex promotion [1], which means the SHA/KEYLOCKER insn does not support EGPR when APX enabled. Update the corresponding constraints to their EGPR-disabled counterparts. Bootstrapped and regtested on x86-64-pc-linux-gnu. Ok for trunk? [1].https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gcc/ChangeLog: * config/i386/sse.md (sha1msg1): Use "ja" instead of "Bm" for memory constraint. (sha1msg2): Likewise. (sha1nexte): Likewise. (sha1rnds4): Likewise. (sha256msg1): Likewise. (sha256msg2): Likewise. (sha256rnds2): Likewise. (aesu8): Use "jm" instead of "m" for memory constraint. (*aesu8): Likewise. (*encodekey128u32): Use "jr" instead of "r" for register constraints. (*encodekey256u32): Likewise. --- gcc/config/i386/sse.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3286d3a4fac..4b8d5342707 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -29104,7 +29104,7 @@ (define_insn "sha1msg1" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm")] + (match_operand:V4SI 2 "vector_operand" "xja")] UNSPEC_SHA1MSG1))] "TARGET_SHA" "sha1msg1\t{%2, %0|%0, %2}" @@ -29115,7 +29115,7 @@ (define_insn "sha1msg2" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm")] + (match_operand:V4SI 2 "vector_operand" "xja")] UNSPEC_SHA1MSG2))] "TARGET_SHA" "sha1msg2\t{%2, %0|%0, %2}" @@ -29126,7 +29126,7 @@ (define_insn "sha1nexte" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm")] + (match_operand:V4SI 2 "vector_operand" "xja")] UNSPEC_SHA1NEXTE))] "TARGET_SHA" "sha1nexte\t{%2, %0|%0, %2}" @@ -29137,7 +29137,7 @@ (define_insn "sha1rnds4" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm") + (match_operand:V4SI 2 "vector_operand" "xja") (match_operand:SI 3 "const_0_to_3_operand")] UNSPEC_SHA1RNDS4))] "TARGET_SHA" @@ -29150,7 +29150,7 @@ (define_insn "sha256msg1" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm")] + (match_operand:V4SI 2 "vector_operand" "xja")] UNSPEC_SHA256MSG1))] "TARGET_SHA" "sha256msg1\t{%2, %0|%0, %2}" @@ -29161,7 +29161,7 @@ (define_insn "sha256msg2" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm")] + (match_operand:V4SI 2 "vector_operand" "xja")] UNSPEC_SHA256MSG2))] "TARGET_SHA" "sha256msg2\t{%2, %0|%0, %2}" @@ -29172,7 +29172,7 @@ (define_insn "sha256rnds2" [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "vector_operand" "xBm") + (match_operand:V4SI 2 "vector_operand" "xja") (match_operand:V4SI 3 "register_operand" "Yz")] UNSPEC_SHA256RNDS2))] "TARGET_SHA" @@ -30575,9 +30575,9 @@ (define_expand "encodekey128u32" (define_insn "*encodekey128u32" [(match_parallel 2 "encodekey128_operation" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=jr") (unspec_volatile:SI - [(match_operand:SI 1 "register_operand" "r") + [(match_operand:SI 1 "register_operand" "jr") (reg:V2DI XMM0_REG)] UNSPECV_ENCODEKEY128U32))])] "TARGET_KL" @@ -30632,9 +30632,9 @@ (define_expand "encodekey256u32" (define_insn "*encodekey256u32" [(match_parallel 2 "encodekey256_operation" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=jr") (unspec_volatile:SI - [(match_operand:SI 1 "register_operand" "r") + [(match_operand:SI 1 "register_operand" "jr") (reg:V2DI XMM0_REG) (reg:V2DI XMM1_REG)] UNSPECV_ENCODEKEY256U32))])] @@ -30655,7 +30655,7 @@ (define_int_attr aesklvariant (define_insn "aesu8" [(set (match_operand:V2DI 0 "register_operand" "=x") (unspec_volatile:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand:BLK 2 "memory_operand" "m")] + (match_operand:BLK 2 "memory_operand" "jm")] AESDECENCKL)) (set (reg:CCZ FLAGS_REG) (unspec_volatile:CCZ [(match_dup 1) (match_dup 2)] AESDECENCKL))] @@ -30719,7 +30719,7 @@ (define_insn "*aesu8" [(match_parallel 1 "aeswidekl_operation" [(set (reg:CCZ FLAGS_REG) (unspec_volatile:CCZ - [(match_operand:BLK 0 "memory_operand" "m")] + [(match_operand:BLK 0 "memory_operand" "jm")] AESDECENCWIDEKL))])] "TARGET_WIDEKL" "aes\t%0"