From patchwork Thu Mar 7 01:12:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 86909 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 075913857C4A for ; Thu, 7 Mar 2024 01:13:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 54E083858D35 for ; Thu, 7 Mar 2024 01:13:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 54E083858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 54E083858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709773994; cv=none; b=nnWYWo6BlJ9yyaGgikm5kQRKms3liEx5rWyiGEOII4NW6uLzQxy581zbaO0EwOhwcrMGDa9ZvjaPQeujUY/FoVih6QsrP6jqBI6nN7SxPh60Vib8id0uhYdb++RS1VGsVhwHAoTlTZQu5tQGaHrUFj+gbovxToaugh9Se2Wpm5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709773994; c=relaxed/simple; bh=fVTFxVEK0LvD/OYELuzf0oNzyIB4aF+LgNf9rXGoJvg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=MtbJbyRl3ywcWvp3RsbGCpR50zunZYoHz7LtiH0vzdCa3GTqhcUTb8EOs+wlLA1e5jlqUjsGG3q9KY5+G6vRemrVlDVv6sbnZN1t42TODQlOtzuMhlrsKQ2brQf3gKkPOhyHqSDJY5X1/Fd255xWF/XPw0RqC26U0qmxDbpjFj0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Cx77uiFOllSngVAA--.33777S3; Thu, 07 Mar 2024 09:13:06 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxdMyZFOllNq1PAA--.31723S2; Thu, 07 Mar 2024 09:13:04 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v1] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi. Date: Thu, 7 Mar 2024 09:12:52 +0800 Message-Id: <20240307011252.11808-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxdMyZFOllNq1PAA--.31723S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxXF1rWw1rKw45Zw1fGFy8WFX_yoWrAF4rpF ZrCw1vgr4kX3ykG397trWUJFnIkrs29ayava97K3409w43AryUXa18t34av3WUCw15Kr1Y vr4Yva4Y9a1UG3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkjb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AK xVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64 vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8G jcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2I x0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK 8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07URa0PUUUUU= X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be implemented through "ll.w+sc.w". In the implementation of the instruction sequence, it is necessary to determine whether the two registers are equal. Since LoongArch's comparison instructions do not distinguish between 32-bit and 64-bit, the two operand registers that need to be compared are symbolically extended, and one of the operand registers is obtained from memory through the "ll.w" instruction, which can ensure that the symbolic expansion is carried out. However, the value of the other operand register is not guaranteed to be the value of the sign extension. gcc/ChangeLog: * config/loongarch/sync.md (atomic_cas_value_strong): In loongarch64, a sign extension operation is added when operands[2] is a register operand and the mode is SImode. gcc/testsuite/ChangeLog: * g++.target/loongarch/atomic-cas-int.C: New test. --- gcc/config/loongarch/sync.md | 46 ++++++++++++++----- .../g++.target/loongarch/atomic-cas-int.C | 32 +++++++++++++ 2 files changed, 67 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/g++.target/loongarch/atomic-cas-int.C diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 8f35a5b48d2..d41c2d26811 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -245,18 +245,42 @@ (define_insn "atomic_cas_value_strong" (clobber (match_scratch:GPR 5 "=&r"))] "" { - return "1:\\n\\t" - "ll.\\t%0,%1\\n\\t" - "bne\\t%0,%z2,2f\\n\\t" - "or%i3\\t%5,$zero,%3\\n\\t" - "sc.\\t%5,%1\\n\\t" - "beqz\\t%5,1b\\n\\t" - "b\\t3f\\n\\t" - "2:\\n\\t" - "%G4\\n\\t" - "3:\\n\\t"; + output_asm_insn ("1:", operands); + output_asm_insn ("ll.\t%0,%1", operands); + + /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the + return value of the val_without_const_folding will not be truncated and + will be passed directly to the function compare_exchange_strong. + However, the instruction 'bne' does not distinguish between 32-bit and + 64-bit operations. so if the upper 32 bits of the register are not + extended by the 32nd bit symbol, then the comparison may not be valid + here. This will affect the result of the operation. */ + + if (TARGET_64BIT && REG_P (operands[2]) + && GET_MODE (operands[2]) == SImode) + { + output_asm_insn ("addi.w\t%5,%2,0", operands); + output_asm_insn ("bne\t%0,%5,2f", operands); + } + else + output_asm_insn ("bne\t%0,%z2,2f", operands); + + output_asm_insn ("or%i3\t%5,$zero,%3", operands); + output_asm_insn ("sc.\t%5,%1", operands); + output_asm_insn ("beqz\t%5,1b", operands); + output_asm_insn ("b\t3f", operands); + output_asm_insn ("2:", operands); + output_asm_insn ("%G4", operands); + output_asm_insn ("3:", operands); + + return ""; } - [(set (attr "length") (const_int 28))]) + [(set (attr "length") + (if_then_else + (and (match_test "GET_MODE (operands[2]) == SImode") + (match_test "REG_P (operands[2])")) + (const_int 32) + (const_int 28)))]) (define_insn "atomic_cas_value_strong_amcas" [(set (match_operand:QHWD 0 "register_operand" "=&r") diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C new file mode 100644 index 00000000000..830ce48267a --- /dev/null +++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include +#include + +__attribute__ ((noinline)) long +val_without_const_folding (long val) +{ + return val; +} + +int +main () +{ + int oldval = 0xaa; + int newval = 0xbb; + std::atomic amo; + + amo.store (oldval); + + long longval = val_without_const_folding (0xff80000000000000 + oldval); + oldval = static_cast (longval); + + amo.compare_exchange_strong (oldval, newval); + + if (newval != amo.load (std::memory_order_relaxed)) + __builtin_abort (); + + return 0; +} +