From patchwork Tue Feb 27 13:56:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 86445 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9E0A138582AD for ; Tue, 27 Feb 2024 13:57:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A198E3858436 for ; Tue, 27 Feb 2024 13:57:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A198E3858436 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A198E3858436 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709042232; cv=none; b=khXiThQ0HpTrmLptUv5U3jPkObdThLiznhx/AY1+zqnAJX55+P/9Ad9kKJrJAtRD6irGy1aCBD4pjGItCnvoQZ3esxzGCWm9p3y/85SkSlEFqc1+D/lApTC6i/uY7mpBJxBWp4zJ5mkILAe13apDGZn/2PLj5mCiLwc+yuEwSw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709042232; c=relaxed/simple; bh=tFVUUH03oXWN/R1Oonponx9PPncVoPa4XWX7xn2T+X0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=LZNkTaHAASterj/BuMc2l4ckWm/pASH9LALURMxtucguc+QPS++JBYTPPUQmuhO0jn+LMTiEDifOtFLDoRR1iKG6z16Iv0ysgOJVYmc4KEWn+c7EMB9ggjjOR6CLQGTxiYipci1gvcDOWWc9mS5K8HB2C+6mcvkv9OXDn3gkZkw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0C621476; Tue, 27 Feb 2024 05:57:48 -0800 (PST) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B174F3F762; Tue, 27 Feb 2024 05:57:09 -0800 (PST) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: stam.markianos-wright@arm.com, richard.earnshaw@arm.com, Andre Vieira Subject: [PATCH v6 3/5] arm: Fix a wrong attribute use and remove unused unspecs and iterators Date: Tue, 27 Feb 2024 13:56:45 +0000 Message-Id: <20240227135647.30404-4-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240227135647.30404-1-andre.simoesdiasvieira@arm.com> References: <20240227135647.30404-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch fixes the erroneous use of a mode attribute without a mode iterator in the pattern and removes unused unspecs and iterators. gcc/ChangeLog: * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U cases. (VMLALDAVXQ): Remove iterator. (VMLALDAVXQ_P): Likewise. (VMLALDAVAXQ): Likewise. * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of mode iterator attribute with V4BI mode. * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U): Remove unused unspecs. --- gcc/config/arm/iterators.md | 9 +++------ gcc/config/arm/mve.md | 2 +- gcc/config/arm/unspecs.md | 3 --- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 22b3ddf5637..3206bcab4cf 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -2370,7 +2370,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u") (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u") - (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s") + (VMLALDAVQ_S "s") (VMLALDAVXQ_S "s") (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u") (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u") (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") @@ -2412,8 +2412,8 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VREV16Q_M_S "s") (VREV16Q_M_U "u") (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u") (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u") - (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u") - (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u") + (VRSHRNBQ_N_U "u") + (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s") (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u") (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s") @@ -2762,7 +2762,6 @@ (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U]) (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U]) (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U]) (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S]) -(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S]) (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S]) (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) @@ -2817,11 +2816,9 @@ (define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U]) (define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S]) (define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S]) (define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U]) -(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S]) (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S]) (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S]) (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S]) -(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U]) (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U]) (define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U]) (define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index d7bdcd862f8..9fe51298cdc 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -4605,7 +4605,7 @@ (define_insn "mve_vstrwq_p_fv4sf" [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") - (match_operand: 2 "vpr_register_operand" "Up") + (match_operand:V4BI 2 "vpr_register_operand" "Up") (match_dup 0)] VSTRWQ_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index b9db306c067..46ac8b37157 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -717,7 +717,6 @@ (define_c_enum "unspec" [ VCVTBQ_F16_F32 VCVTTQ_F16_F32 VMLALDAVQ_U - VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S VMLSLDAVQ_S @@ -934,7 +933,6 @@ (define_c_enum "unspec" [ VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U - VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S @@ -943,7 +941,6 @@ (define_c_enum "unspec" [ VQSHRNTQ_N_U VQSHRNTQ_N_S VMLALDAVAXQ_S - VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U VCVTBQ_M_F16_F32