From patchwork Wed Jan 17 09:00:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 84231 X-Patchwork-Delegate: juzhe.zhong@rivai.ai Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3F05C3858C33 for ; Wed, 17 Jan 2024 09:01:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by sourceware.org (Postfix) with ESMTPS id A832B3858CDB for ; Wed, 17 Jan 2024 09:01:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A832B3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A832B3858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705482067; cv=none; b=A4Gqlc5V5/8ro/4J9tY6vvTa3czjAhejLG9OWtyaz9C+jgaLcBLqUYyX42buQ1gCPJAvADXns4Jq09o4iLhp7XjIcVz80FbGv2WpPb0b3GDmLHun/kIuhC9v4ky0ikXK0FCdqi4HVDcF+DxL5lmpO39Esl0NZVobJpcSFZqp82I= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705482067; c=relaxed/simple; bh=MT40YYZgQdVD6JrrNSvmkNyx8DjcdkywqsLecMAxJHA=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=XS0ORZlO/u1EughZd4H+KMIS5/tdP5ZsDwERy1TiqW9i6nTjUDIxr8f54SNHE5E3T1iqKWclnuhRvz9/dPbSBiZI7+7Y94DEYt2jk/9eOQYAMvKbAhKlPiYQj3AR1TiRsXytaZWbpPOHv9Oe9AyJaKktrOocxzsPO5LnFvrlEcw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705482062; x=1737018062; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MT40YYZgQdVD6JrrNSvmkNyx8DjcdkywqsLecMAxJHA=; b=RdyfMCf8xJBnzHVS9edEvPu1spDov0Ulrk1JpYlAeXgHVxVgv+iZEuOu ANYETG35abQGm5OMxFpsGy3a2gO41IlUTyVWyExPZPcFRYN2018G8ho7B Eib08+pPi+cWdZ4gq7EO+RUk8y+qRRPk4szS5BcWiROwE1mMD2U0L1ZHf Awb+B9TU4FcTFykMs+tYsLfbcmboWs7YQ3Gk9sep273DAsi+SHdB4GFaV rJBAMHwqlhYtoWC/VZKAEeeQOp7BLNQv84PaiYVlyQgu2uU8nIhobEH12 0F+/cFka/x2mGmy0tQuPqtEe1ZUrhmUpHu5UApdEu84647Tl3qLmC1zsU Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10955"; a="6872024" X-IronPort-AV: E=Sophos;i="6.05,200,1701158400"; d="scan'208";a="6872024" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2024 01:01:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,200,1701158400"; d="scan'208";a="32757073" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa001.jf.intel.com with ESMTP; 17 Jan 2024 01:00:57 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 098F9100568A; Wed, 17 Jan 2024 17:00:57 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Fix asm checks regression due to recent middle-end change Date: Wed, 17 Jan 2024 17:00:55 +0800 Message-Id: <20240117090055.763458-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Pan Li The recent middle-end change result in some asm check failures. This patch would like to fix the asm check by adjust the times. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/shift-1.c: Fix asm check count. * gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c index e57a0b6bdf3..cb5a1dbc9ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>) DEF_OP_VV (shift, 256, int64_t, >>) DEF_OP_VV (shift, 512, int64_t, >>) -/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c index 9d1fa64232c..e626a52c2d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>) DEF_OP_VV (shift, 256, uint64_t, >>) DEF_OP_VV (shift, 512, uint64_t, >>) -/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c index 8de1b9c0c41..244bee02e55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, <<) DEF_OP_VV (shift, 256, int64_t, <<) DEF_OP_VV (shift, 512, int64_t, <<) -/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 46 } } */ +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */ /* { dg-final { scan-assembler-not {csrr} } } */