From patchwork Mon Dec 18 13:43:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 82388 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 866633857C46 for ; Mon, 18 Dec 2023 13:44:44 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 3400F385828F for ; Mon, 18 Dec 2023 13:44:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3400F385828F Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3400F385828F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702907069; cv=none; b=hgveqhLqfW+G/LfeHjceDO34SupNxJdI1HGDiRmm0fKIth4jf7A+H+eVbqowQg/E3nkEF2BhSAgvc6ER3RuOhY7E+Eu718C254PaOwETg5UtrxOi2Pk/P373l1P+nev0fx0NGODOUOeWwIefHqFu5A2t/AriZYMUNgphO/GAq54= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702907069; c=relaxed/simple; bh=xpSDlaxLTKr6TzTdY4IzWi+dSCSw7r0FTwJWywLqo78=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=st6aSW7Tp/5irryZpIHQ0Of1LhLYd4kpGLTl4YAQztmVkW8EN0jSqAismsk+ud31H+FhnmVvPqFvT663mfbJXayU86ydq0GbgiDkb5pW5Pwc3PxICxSAtOvYDa0LqoOCLR0vrKTe3XwTiqH7FO+4loDw7b4voO+JOyJiB26kJUM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1702907067; bh=xpSDlaxLTKr6TzTdY4IzWi+dSCSw7r0FTwJWywLqo78=; h=From:To:Cc:Subject:Date:From; b=GwrxN9U0TlQiZRNidIZ6drV4AxtKF/stzwbYalO+lPm4khXrnH5ld6QWgv1v4dl3Q 9szcMpz6UTY+5FLmy/1DniUnOMZs9mzFO6PrbGsE/GoBPvbP7YVR7njks1mC9MVqh6 5YQ1ZYvBuRjoNeIos/rhdsFHoZ0RQfL/Y4+Ji/DI= Received: from stargazer.. (unknown [113.200.174.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id D53D5670CE; Mon, 18 Dec 2023 08:44:25 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, c@jia.je, Xi Ruoyao Subject: [PATCH] LoongArch: Expand left rotate to right rotate with negated amount Date: Mon, 18 Dec 2023 21:43:43 +0800 Message-ID: <20231218134414.1513666-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/loongarch.md (rotl3): New define_expand. * config/loongarch/simd.md (vrotl3): Likewise. (rotl3): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/rotl-with-rotr.c: New test. * gcc.target/loongarch/rotl-with-vrotr.c: New test. * gcc.target/loongarch/rotl-with-xvrotr.c: New test. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/loongarch.md | 12 ++++++++ gcc/config/loongarch/simd.md | 29 +++++++++++++++++++ .../gcc.target/loongarch/rotl-with-rotr.c | 9 ++++++ .../gcc.target/loongarch/rotl-with-vrotr.c | 24 +++++++++++++++ .../gcc.target/loongarch/rotl-with-xvrotr.c | 7 +++++ 5 files changed, 81 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 30025bf1908..939432b83e0 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2903,6 +2903,18 @@ (define_insn "rotrsi3_extend" [(set_attr "type" "shift,shift") (set_attr "mode" "SI")]) +;; Expand left rotate to right rotate. +(define_expand "rotl3" + [(set (match_dup 3) + (neg:SI (match_operand:SI 2 "register_operand"))) + (set (match_operand:GPR 0 "register_operand") + (rotatert:GPR (match_operand:GPR 1 "register_operand") + (match_dup 3)))] + "" + { + operands[3] = gen_reg_rtx (SImode); + }); + ;; The following templates were added to generate "bstrpick.d + alsl.d" ;; instruction pairs. ;; It is required that the values of const_immalsl_operand and diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 13202f79bee..a42e20eb8fc 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -268,6 +268,35 @@ (define_insn "vrotr3" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) +;; Expand left rotate to right rotate. +(define_expand "vrotl3" + [(set (match_dup 3) + (neg:IVEC (match_operand:IVEC 2 "register_operand"))) + (set (match_operand:IVEC 0 "register_operand") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") + (match_dup 3)))] + "" + { + operands[3] = gen_reg_rtx (mode); + }); + +;; Expand left rotate with a scalar amount to right rotate: negate the +;; scalar before broadcasting it because scalar negation is cheaper than +;; vector negation. +(define_expand "rotl3" + [(set (match_dup 3) + (neg:SI (match_operand:SI 2 "register_operand"))) + (set (match_dup 4) + (vec_duplicate:IVEC (match_dup 3))) + (set (match_operand:IVEC 0 "register_operand") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") + (match_dup 4)))] + "" + { + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (mode); + }); + ;; vrotri.{b/h/w/d} (define_insn "rotr3" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c new file mode 100644 index 00000000000..84cc53cecaf --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "rotr\\.w" } } */ + +unsigned +t (unsigned a, unsigned b) +{ + return a << b | a >> (32 - b); +} diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c new file mode 100644 index 00000000000..3ebf7e3c083 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "vrotr\\.w" 2 } } */ +/* { dg-final { scan-assembler-times "vneg\\.w" 1 } } */ + +#ifndef VLEN +#define VLEN 16 +#endif + +typedef unsigned int V __attribute__((vector_size(VLEN))); +V a, b, c; + +void +test (int x) +{ + b = a << x | a >> (32 - x); +} + +void +test2 (void) +{ + for (int i = 0; i < VLEN / sizeof (int); i++) + c[i] = a[i] << b[i] | a[i] >> (32 - b[i]); +} diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c new file mode 100644 index 00000000000..833e041b2e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "xvrotr\\.w" 2 } } */ +/* { dg-final { scan-assembler-times "xvneg\\.w" 1 } } */ + +#define VLEN 32 +#include "rotl-with-vrotr.c"