From patchwork Mon Dec 18 07:04:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 82371 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E837938582B6 for ; Mon, 18 Dec 2023 07:05:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id EE0943858424 for ; Mon, 18 Dec 2023 07:04:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE0943858424 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EE0943858424 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.126 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702883081; cv=none; b=T0ULKU71zQDkx+5UOK0/BssI/YlaYkHLWAhecpcbpcKjYcBvqb7LbMdykFAr1pv2YUOtk4KPGK9QkeUCph8NRUrs91C5Z5KYwfwpbXR346oN2YYxQBkQQpBue9rpKxoe6pcZxwPF3CPYwHhHzcOZJ1Syz3kCRDxIoM0jderrKCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702883081; c=relaxed/simple; bh=PME7L+A7HY0tV3g1PlN6lG2uwtYKtrrFWiVb39nrZdU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=fIq/pEIffl2at32daUlgMzzL0xpfayL8oIuqKzxS0286liu73OkLmvrht150EGjwvPQvRgUFuWeGHwxCIooMgA9u5APpffov2ZvQyVNPN/GPuOmPotjq06nuulqnXcB2sRrhmki3btLLQ1p2KlrTPpKbPg9v+xJd7NmN8gj/Eqk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702883079; x=1734419079; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PME7L+A7HY0tV3g1PlN6lG2uwtYKtrrFWiVb39nrZdU=; b=bbDZRC72Tp3e13iU+h1E364mVu28iFvBdHg1ljX2qxjm63Md7zC6Qjbn 8zoVpaxUjc0GF1yZCw8YirfmOC3MLPkrHpmhUhAmUSQgm/8iY3r+JAEAE vHTiOpEOm45XnGTYv+HVMRubk3vRd/0zZWscdGLkQIc86WM8IOiV+QjvF 88JjjUMmu/V0sYCAsp/Ugzusidnit2BWHkhqW9RYbExDNpf27/20tjR3y P9gxVaIOuECoMiyAilqRxCC73o491/PTAE6qnRNShJdy2DWfvlToaaKj0 YHT3WpbaSuEY243CgHZzyBvO1SAAqU3JQlUvuCw4pin4sOakPwAV4OclC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="380452536" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="380452536" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2023 23:04:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="725208757" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="725208757" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 17 Dec 2023 23:04:36 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 37CD3100581C; Mon, 18 Dec 2023 15:04:35 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for the RVV const vector Date: Mon, 18 Dec 2023 15:04:33 +0800 Message-Id: <20231218070433.2000339-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to fix one bug of const vector for interleave. Assume we need to generate interleave const vector like below. V = {{4, -4, 3, -3, 2, -2, 1, -1,} Before this patch: vsetvl a3, zero, e64, m8, ta, ma vid.v v8 v8 = {0, 1, 2, 3, 4} li a6, -1 vmul.vx v8, v8, a6 v8 = {-0, -1, -2, -3, -4} vadd.vi v24, v8, 4 v24 = { 4, 3, 2, 1, 0} vadd.vi v8, v8, -4 v8 = {-4, -5, -6, -7, -8} li a6, 32 vsll.vx v8, v8, a6 v8 = {0, -4, 0, -5, 0, -6, 0, -7,} for e32 vor v24, v24, v8 v24 = {4, -4, 3, -5, 2, -6, 1, -7,} for e32 After this patch: vsetvli a6,zero,e64,m8,ta,ma vidv v8 v8 = {0, 1, 2, 3, 4} li a7,-1 vmul.vx v16,v8,a7 v16 = {-0, -1, -2, -3, -4} vaddvi v16,v16,4 v16 = { 4, 3, 2, 1, 0} vaddvi v8,v8,-4 v8 = {-4, -3, -2, -1, 0} li a7,32 vsll.vx v8,v8,a7 v8 = {0, -4, 0, -3, 0, -2,} for e32 vor.vv v16,v16,v8 v8 = {4, -4, 3, -3, 2, -2,} for e32 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Take step2 instead of step1 for second series. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/const-vector-0.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 2 +- .../riscv/rvv/autovec/const-vector-0.c | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/const-vector-0.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index eade8db4cf1..d1eb7a0a9a5 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1331,7 +1331,7 @@ expand_const_vector (rtx target, rtx src) rtx tmp2 = gen_reg_rtx (new_mode); base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode); expand_vec_series (tmp2, base2, - gen_int_mode (step1, new_smode)); + gen_int_mode (step2, new_smode)); rtx shifted_tmp2 = expand_simple_binop ( new_mode, ASHIFT, tmp2, gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/const-vector-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/const-vector-0.c new file mode 100644 index 00000000000..4f83121c663 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/const-vector-0.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -ftree-vectorize -fno-vect-cost-model -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define N 4 +struct C { int r, i; }; + +/* +** init_struct_data: +** ... +** vsetivli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m8,\s*ta,\s*ma +** vid\.v\s+v8 +** li\s+[atx][0-9]+,\s*-1 +** vmul\.vx\s+v16,\s*v8,\s*[atx][0-9]+ +** vadd\.vi\s+v16,\s*v16,\s*4 +** vadd\.vi\s+v8,\s*v8,\s*-4 +** li\s+[axt][0-9]+,32 +** vsll\.vx\s+v8,\s*v8,\s*[atx][0-9]+ +** vor\.vv\s+v16,\s*v16,\s*v8 +** ... +*/ +void +init_struct_data (struct C * __restrict a, struct C * __restrict b, + struct C * __restrict c) +{ + int i; + + for (i = 0; i < N; ++i) + { + a[i].r = N - i; + a[i].i = i - N; + + b[i].r = i - N; + b[i].i = i + N; + + c[i].r = -1 - i; + c[i].i = 2 * N - 1 - i; + } +}