From patchwork Sun Dec 17 15:12:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 82333 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CF2593858D39 for ; Sun, 17 Dec 2023 15:13:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id C7E263858D39 for ; Sun, 17 Dec 2023 15:13:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C7E263858D39 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C7E263858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702826016; cv=none; b=FeX1jIU43z/vFkxXKyI+pqOofS4TcwljeltIf1RpCdxW39DiITUB5zmz9Hl232nUfqfJtjPOS8PE6C9JHyZylo3AJIdEBvWDnwGQbs/FAlOQsFq0f/e3ESwmd7zk7xIcQ91xEyGq+wAE+1X5n4Pky9Z9d40ihTTE5CpeuexfeQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702826016; c=relaxed/simple; bh=5kaw2ACqrzJOX7G7O1cR13TlV40X/oN2gl99GpLZNg8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Bkl/yzui/+5Yi+PAzNY9ZQ/wP4e+r64XTukKEw+MGiy0In1mLTvcc96+sOT7byQFhy6sTlN73t/g46SsVgnyjGl5XF/gM8WQ1J1tNzpVy4RwinY0K+Bo36qgps2ZL4qKvSd9KrVQJp9rF3gEVD5dtWfqAqL2OQ/fnuCQCbB87yY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1702826008; bh=5kaw2ACqrzJOX7G7O1cR13TlV40X/oN2gl99GpLZNg8=; h=From:To:Cc:Subject:Date:From; b=Hkjd/44IVtxE/6JYTvAJ3DEnyizd7YW/x5wcEKdWJAEcZaEDND/XDig/qutWM4XYC 1a5/exahrCHLYQJ8KjaP4kXuW9k2Ybw5CereFPlqwDS3j6XMwImz/kaM0o9K84sG8t fv24PWpzucO3pLG2CJVCP3TnmnERkcc0cA7WbXY8= Received: from stargazer.. (unknown [IPv6:240e:358:11ec:9900:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 9240F66DD7; Sun, 17 Dec 2023 10:13:24 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Jiahao Xu , c@jia.je, Xi Ruoyao Subject: [PATCH] LoongArch: Fix FP vector comparsons [PR113034] Date: Sun, 17 Dec 2023 23:12:18 +0800 Message-ID: <20231217151309.4128-2-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org We had the following mappings between vfcmp submenmonics and RTX codes: (define_code_attr fcc [(unordered "cun") (ordered "cor") (eq "ceq") (ne "cne") (uneq "cueq") (unle "cule") (unlt "cult") (le "cle") (lt "clt")]) This is inconsistent with scalar code: (define_code_attr fcond [(unordered "cun") (uneq "cueq") (unlt "cult") (unle "cule") (eq "ceq") (lt "slt") (le "sle") (ordered "cor") (ltgt "sne") (ne "cune") (ge "sge") (gt "sgt") (unge "cuge") (ungt "cugt")]) For every RTX code for which the LSX/LASX code is different from the scalar code, the scalar code is correct and the LSX/LASX code is wrong. Most seriously, the RTX code NE should be mapped to "cneq", not "cne". Rewrite vfcmp define_insns in simd.md using the same mapping as scalar fcmp. Note that GAS does not support [x]vfcmp.{c/s}[u]{ge/gt} (pseudo) instruction (although fcmp.{c/s}[u]{ge/gt} is supported), so we need to switch the order of inputs and use [x]vfcmp.{c/s}[u]{le/lt} instead. The vfcmp.{sult/sule/clt/cle}.{s/d} instructions do not have a single RTX code, but they can be modeled as an inversed RTX code following a "not" operation. Doing so allows the compiler to optimized vectorized __builtin_isless etc. to a single instruction. This optimization should be added for scalar code too and I'll do it later. Tests are added for mapping between C code, IEC 60559 operations, and vfcmp instructions. [1]:https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640713.html gcc/ChangeLog: PR target/113034 * config/loongarch/lasx.md (UNSPEC_LASX_XVFCMP_*): Remove. (lasx_xvfcmp_caf_): Remove. (lasx_xvfcmp_cune_): Remove. (FSC256_UNS): Remove. (fsc256): Remove. (lasx_xvfcmp__): Remove. (lasx_xvfcmp__): Remove. * config/loongarch/lsx.md (UNSPEC_LSX_XVFCMP_*): Remove. (lsx_vfcmp_caf_): Remove. (lsx_vfcmp_cune_): Remove. (vfcond): Remove. (fcc): Remove. (FSC_UNS): Remove. (fsc): Remove. (lsx_vfcmp__): Remove. (lsx_vfcmp__): Remove. * config/loongarch/simd.md (fcond_simd): New define_code_iterator. (_vfcmp__): New define_insn. (fcond_simd_rev): New define_code_iterator. (fcond_rev_asm): New define_code_attr. (_vfcmp__): New define_insn. (fcond_inv): New define_code_iterator. (fcond_inv_rev): New define_code_iterator. (fcond_inv_rev_asm): New define_code_attr. (_vfcmp__): New define_insn. (_vfcmp__): New define_insn. (UNSPEC_SIMD_FCMP_CAF, UNSPEC_SIMD_FCMP_SAF, UNSPEC_SIMD_FCMP_SEQ, UNSPEC_SIMD_FCMP_SUN, UNSPEC_SIMD_FCMP_SUEQ, UNSPEC_SIMD_FCMP_CNE, UNSPEC_SIMD_FCMP_SOR, UNSPEC_SIMD_FCMP_SUNE): New unspecs. (SIMD_FCMP): New define_int_iterator. (fcond_unspec): New define_int_attr. (_vfcmp__): New define_insn. * config/loongarch/loongarch.cc (loongarch_expand_lsx_cmp): Remove unneeded special cases. gcc/testsuite/ChangeLog: PR target/113034 * gcc.target/loongarch/vfcmp-f.c: New test. * gcc.target/loongarch/vfcmp-d.c: New test. * gcc.target/loongarch/xvfcmp-f.c: New test. * gcc.target/loongarch/xvfcmp-d.c: New test. * gcc.target/loongarch/vector/lasx/lasx-vcond-2.c: Scan for cune instead of cne. * gcc.target/loongarch/vector/lsx/lsx-vcond-2.c: Likewise. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/lasx.md | 76 -------- gcc/config/loongarch/loongarch.cc | 60 +----- gcc/config/loongarch/lsx.md | 83 -------- gcc/config/loongarch/simd.md | 118 ++++++++++++ .../loongarch/vector/lasx/lasx-vcond-2.c | 4 +- .../loongarch/vector/lsx/lsx-vcond-2.c | 4 +- gcc/testsuite/gcc.target/loongarch/vfcmp-d.c | 28 +++ gcc/testsuite/gcc.target/loongarch/vfcmp-f.c | 178 ++++++++++++++++++ gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c | 29 +++ gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c | 27 +++ 10 files changed, 385 insertions(+), 222 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vfcmp-d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vfcmp-f.c create mode 100644 gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index eeac8cd984b..921ce0eebed 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -32,9 +32,7 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVBITREVI UNSPEC_LASX_XVBITSET UNSPEC_LASX_XVBITSETI - UNSPEC_LASX_XVFCMP_CAF UNSPEC_LASX_XVFCLASS - UNSPEC_LASX_XVFCMP_CUNE UNSPEC_LASX_XVFCVT UNSPEC_LASX_XVFCVTH UNSPEC_LASX_XVFCVTL @@ -44,17 +42,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVFRINT UNSPEC_LASX_XVFRSQRT UNSPEC_LASX_XVFRSQRTE - UNSPEC_LASX_XVFCMP_SAF - UNSPEC_LASX_XVFCMP_SEQ - UNSPEC_LASX_XVFCMP_SLE - UNSPEC_LASX_XVFCMP_SLT - UNSPEC_LASX_XVFCMP_SNE - UNSPEC_LASX_XVFCMP_SOR - UNSPEC_LASX_XVFCMP_SUEQ - UNSPEC_LASX_XVFCMP_SULE - UNSPEC_LASX_XVFCMP_SULT - UNSPEC_LASX_XVFCMP_SUN - UNSPEC_LASX_XVFCMP_SUNE UNSPEC_LASX_XVFTINT_U UNSPEC_LASX_XVCLO UNSPEC_LASX_XVSAT_S @@ -1481,69 +1468,6 @@ (define_insn "lasx_xvfclass_" [(set_attr "type" "simd_fclass") (set_attr "mode" "")]) -(define_insn "lasx_xvfcmp_caf_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLASX 1 "register_operand" "f") - (match_operand:FLASX 2 "register_operand" "f")] - UNSPEC_LASX_XVFCMP_CAF))] - "ISA_HAS_LASX" - "xvfcmp.caf.\t%u0,%u1,%u2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - -(define_insn "lasx_xvfcmp_cune_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLASX 1 "register_operand" "f") - (match_operand:FLASX 2 "register_operand" "f")] - UNSPEC_LASX_XVFCMP_CUNE))] - "ISA_HAS_LASX" - "xvfcmp.cune.\t%u0,%u1,%u2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - - - -(define_int_iterator FSC256_UNS [UNSPEC_LASX_XVFCMP_SAF UNSPEC_LASX_XVFCMP_SUN - UNSPEC_LASX_XVFCMP_SOR UNSPEC_LASX_XVFCMP_SEQ - UNSPEC_LASX_XVFCMP_SNE UNSPEC_LASX_XVFCMP_SUEQ - UNSPEC_LASX_XVFCMP_SUNE UNSPEC_LASX_XVFCMP_SULE - UNSPEC_LASX_XVFCMP_SULT UNSPEC_LASX_XVFCMP_SLE - UNSPEC_LASX_XVFCMP_SLT]) - -(define_int_attr fsc256 - [(UNSPEC_LASX_XVFCMP_SAF "saf") - (UNSPEC_LASX_XVFCMP_SUN "sun") - (UNSPEC_LASX_XVFCMP_SOR "sor") - (UNSPEC_LASX_XVFCMP_SEQ "seq") - (UNSPEC_LASX_XVFCMP_SNE "sne") - (UNSPEC_LASX_XVFCMP_SUEQ "sueq") - (UNSPEC_LASX_XVFCMP_SUNE "sune") - (UNSPEC_LASX_XVFCMP_SULE "sule") - (UNSPEC_LASX_XVFCMP_SULT "sult") - (UNSPEC_LASX_XVFCMP_SLE "sle") - (UNSPEC_LASX_XVFCMP_SLT "slt")]) - -(define_insn "lasx_xvfcmp__" - [(set (match_operand: 0 "register_operand" "=f") - (vfcond: (match_operand:FLASX 1 "register_operand" "f") - (match_operand:FLASX 2 "register_operand" "f")))] - "ISA_HAS_LASX" - "xvfcmp..\t%u0,%u1,%u2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - - -(define_insn "lasx_xvfcmp__" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLASX 1 "register_operand" "f") - (match_operand:FLASX 2 "register_operand" "f")] - FSC256_UNS))] - "ISA_HAS_LASX" - "xvfcmp..\t%u0,%u1,%u2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - - (define_mode_attr fint256 [(V8SF "v8si") (V4DF "v4di")]) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index d7fd203c1ab..256fa7d048d 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -11181,7 +11181,6 @@ static void loongarch_expand_lsx_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1) { machine_mode cmp_mode = GET_MODE (op0); - int unspec = -1; bool negate = false; switch (cmp_mode) @@ -11223,66 +11222,9 @@ loongarch_expand_lsx_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1) case E_V4SFmode: case E_V2DFmode: - switch (cond) - { - case UNORDERED: - case ORDERED: - case EQ: - case NE: - case UNEQ: - case UNLE: - case UNLT: - break; - case LTGT: cond = NE; break; - case UNGE: cond = UNLE; std::swap (op0, op1); break; - case UNGT: cond = UNLT; std::swap (op0, op1); break; - case LE: unspec = UNSPEC_LSX_VFCMP_SLE; break; - case LT: unspec = UNSPEC_LSX_VFCMP_SLT; break; - case GE: unspec = UNSPEC_LSX_VFCMP_SLE; std::swap (op0, op1); break; - case GT: unspec = UNSPEC_LSX_VFCMP_SLT; std::swap (op0, op1); break; - default: - gcc_unreachable (); - } - if (unspec < 0) - loongarch_emit_binary (cond, dest, op0, op1); - else - { - rtx x = gen_rtx_UNSPEC (GET_MODE (dest), - gen_rtvec (2, op0, op1), unspec); - emit_insn (gen_rtx_SET (dest, x)); - } - break; - case E_V8SFmode: case E_V4DFmode: - switch (cond) - { - case UNORDERED: - case ORDERED: - case EQ: - case NE: - case UNEQ: - case UNLE: - case UNLT: - break; - case LTGT: cond = NE; break; - case UNGE: cond = UNLE; std::swap (op0, op1); break; - case UNGT: cond = UNLT; std::swap (op0, op1); break; - case LE: unspec = UNSPEC_LASX_XVFCMP_SLE; break; - case LT: unspec = UNSPEC_LASX_XVFCMP_SLT; break; - case GE: unspec = UNSPEC_LASX_XVFCMP_SLE; std::swap (op0, op1); break; - case GT: unspec = UNSPEC_LASX_XVFCMP_SLT; std::swap (op0, op1); break; - default: - gcc_unreachable (); - } - if (unspec < 0) - loongarch_emit_binary (cond, dest, op0, op1); - else - { - rtx x = gen_rtx_UNSPEC (GET_MODE (dest), - gen_rtvec (2, op0, op1), unspec); - emit_insn (gen_rtx_SET (dest, x)); - } + loongarch_emit_binary (cond, dest, op0, op1); break; default: diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index dbdb423011b..57e0ee3d44d 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -34,9 +34,7 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VBITSETI UNSPEC_LSX_BRANCH_V UNSPEC_LSX_BRANCH - UNSPEC_LSX_VFCMP_CAF UNSPEC_LSX_VFCLASS - UNSPEC_LSX_VFCMP_CUNE UNSPEC_LSX_VFCVT UNSPEC_LSX_VFCVTH UNSPEC_LSX_VFCVTL @@ -46,17 +44,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VFRINT UNSPEC_LSX_VFRSQRT UNSPEC_LSX_VFRSQRTE - UNSPEC_LSX_VFCMP_SAF - UNSPEC_LSX_VFCMP_SEQ - UNSPEC_LSX_VFCMP_SLE - UNSPEC_LSX_VFCMP_SLT - UNSPEC_LSX_VFCMP_SNE - UNSPEC_LSX_VFCMP_SOR - UNSPEC_LSX_VFCMP_SUEQ - UNSPEC_LSX_VFCMP_SULE - UNSPEC_LSX_VFCMP_SULT - UNSPEC_LSX_VFCMP_SUN - UNSPEC_LSX_VFCMP_SUNE UNSPEC_LSX_VFTINT_U UNSPEC_LSX_VSAT_S UNSPEC_LSX_VSAT_U @@ -1377,76 +1364,6 @@ (define_insn "lsx_vfclass_" [(set_attr "type" "simd_fclass") (set_attr "mode" "")]) -(define_insn "lsx_vfcmp_caf_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLSX 1 "register_operand" "f") - (match_operand:FLSX 2 "register_operand" "f")] - UNSPEC_LSX_VFCMP_CAF))] - "ISA_HAS_LSX" - "vfcmp.caf.\t%w0,%w1,%w2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - -(define_insn "lsx_vfcmp_cune_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLSX 1 "register_operand" "f") - (match_operand:FLSX 2 "register_operand" "f")] - UNSPEC_LSX_VFCMP_CUNE))] - "ISA_HAS_LSX" - "vfcmp.cune.\t%w0,%w1,%w2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - -(define_code_iterator vfcond [unordered ordered eq ne le lt uneq unle unlt]) - -(define_code_attr fcc - [(unordered "cun") - (ordered "cor") - (eq "ceq") - (ne "cne") - (uneq "cueq") - (unle "cule") - (unlt "cult") - (le "cle") - (lt "clt")]) - -(define_int_iterator FSC_UNS [UNSPEC_LSX_VFCMP_SAF UNSPEC_LSX_VFCMP_SUN UNSPEC_LSX_VFCMP_SOR - UNSPEC_LSX_VFCMP_SEQ UNSPEC_LSX_VFCMP_SNE UNSPEC_LSX_VFCMP_SUEQ - UNSPEC_LSX_VFCMP_SUNE UNSPEC_LSX_VFCMP_SULE UNSPEC_LSX_VFCMP_SULT - UNSPEC_LSX_VFCMP_SLE UNSPEC_LSX_VFCMP_SLT]) - -(define_int_attr fsc - [(UNSPEC_LSX_VFCMP_SAF "saf") - (UNSPEC_LSX_VFCMP_SUN "sun") - (UNSPEC_LSX_VFCMP_SOR "sor") - (UNSPEC_LSX_VFCMP_SEQ "seq") - (UNSPEC_LSX_VFCMP_SNE "sne") - (UNSPEC_LSX_VFCMP_SUEQ "sueq") - (UNSPEC_LSX_VFCMP_SUNE "sune") - (UNSPEC_LSX_VFCMP_SULE "sule") - (UNSPEC_LSX_VFCMP_SULT "sult") - (UNSPEC_LSX_VFCMP_SLE "sle") - (UNSPEC_LSX_VFCMP_SLT "slt")]) - -(define_insn "lsx_vfcmp__" - [(set (match_operand: 0 "register_operand" "=f") - (vfcond: (match_operand:FLSX 1 "register_operand" "f") - (match_operand:FLSX 2 "register_operand" "f")))] - "ISA_HAS_LSX" - "vfcmp..\t%w0,%w1,%w2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - -(define_insn "lsx_vfcmp__" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLSX 1 "register_operand" "f") - (match_operand:FLSX 2 "register_operand" "f")] - FSC_UNS))] - "ISA_HAS_LSX" - "vfcmp..\t%w0,%w1,%w2" - [(set_attr "type" "simd_fcmp") - (set_attr "mode" "")]) - (define_mode_attr fint [(V4SF "v4si") (V2DF "v2di")]) diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 843b1a41f31..13202f79bee 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -279,6 +279,124 @@ (define_insn "rotr3" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) +;; vfcmp.*.{s/d} with defined RTX code +;; There are no fcmp.{sugt/suge/cgt/cge}.{s/d} menmonics in GAS, so we have +;; to reverse the operands ourselves :(. +(define_code_iterator fcond_simd [unordered uneq unlt unle eq lt le + ordered ltgt ne]) +(define_insn "_vfcmp__" + [(set (match_operand: 0 "register_operand" "=f") + (fcond_simd: + (match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f")))] + "" + "vfcmp..\t%0,%1,%2" + [(set_attr "type" "simd_fcmp") + (set_attr "mode" "")]) + +;; There are no fcmp.{sge/sgt/cuge/cugt}.{s/d} menmonics in GAS, so we have +;; to reverse the operands ourselves. +(define_code_iterator fcond_simd_rev [ge gt unge ungt]) + +(define_code_attr fcond_rev_asm + [(ge "sle") + (gt "slt") + (unge "cule") + (ungt "cult")]) + +(define_insn "_vfcmp__" + [(set (match_operand: 0 "register_operand" "=f") + (fcond_simd_rev: + (match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f")))] + "" + "vfcmp..\t%0,%2,%1"; + [(set_attr "type" "simd_fcmp") + (set_attr "mode" "")]) + +;; vfcmp.*.{s/d} without defined RTX code, but with defined RTX code for +;; its inverse. Again, there are no fcmp.{sugt/suge/cgt/cge}.{s/d} +;; menmonics in GAS, so we have to reverse the operands ourselves. +(define_code_iterator fcond_inv [ge gt unge ungt]) +(define_code_iterator fcond_inv_rev [le lt unle unlt]) +(define_code_attr fcond_inv + [(ge "sult") + (gt "sule") + (unge "clt") + (ungt "cle") + (le "sugt") + (lt "suge") + (unle "cgt") + (unlt "cge")]) +(define_code_attr fcond_inv_rev_asm + [(le "sult") + (lt "sule") + (unle "clt") + (unlt "cle")]) + +(define_insn "_vfcmp__" + [(set (match_operand: 0 "register_operand" "=f") + (not: + (fcond_inv: + (match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f"))))] + "" + "vfcmp..\t%0,%1,%2" + [(set_attr "type" "simd_fcmp") + (set_attr "mode" "")]) + +(define_insn "_vfcmp__" + [(set (match_operand: 0 "register_operand" "=f") + (not: + (fcond_inv_rev: + (match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f"))))] + "" + "vfcmp..\t%0,%2,%1" + [(set_attr "type" "simd_fcmp") + (set_attr "mode" "")]) + +;; vfcmp.*.{s/d} instructions only as instrinsics +(define_c_enum "unspec" + [UNSPEC_SIMD_FCMP_CAF + UNSPEC_SIMD_FCMP_SAF + UNSPEC_SIMD_FCMP_SEQ + UNSPEC_SIMD_FCMP_SUN + UNSPEC_SIMD_FCMP_SUEQ + UNSPEC_SIMD_FCMP_CNE + UNSPEC_SIMD_FCMP_SOR + UNSPEC_SIMD_FCMP_SUNE]) + +(define_int_iterator SIMD_FCMP + [UNSPEC_SIMD_FCMP_CAF + UNSPEC_SIMD_FCMP_SAF + UNSPEC_SIMD_FCMP_SEQ + UNSPEC_SIMD_FCMP_SUN + UNSPEC_SIMD_FCMP_SUEQ + UNSPEC_SIMD_FCMP_CNE + UNSPEC_SIMD_FCMP_SOR + UNSPEC_SIMD_FCMP_SUNE]) + +(define_int_attr fcond_unspec + [(UNSPEC_SIMD_FCMP_CAF "caf") + (UNSPEC_SIMD_FCMP_SAF "saf") + (UNSPEC_SIMD_FCMP_SEQ "seq") + (UNSPEC_SIMD_FCMP_SUN "sun") + (UNSPEC_SIMD_FCMP_SUEQ "sueq") + (UNSPEC_SIMD_FCMP_CNE "cne") + (UNSPEC_SIMD_FCMP_SOR "sor") + (UNSPEC_SIMD_FCMP_SUNE "sune")]) + +(define_insn "_vfcmp__" + [(set (match_operand: 0 "register_operand" "=f") + (unspec: [(match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f")] + SIMD_FCMP))] + "" + "vfcmp..\t%0,%1,%2" + [(set_attr "type" "simd_fcmp") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c index 55d5a084c88..f2f523622bc 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c @@ -69,8 +69,8 @@ TEST_CMP (nugt) /* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.s} 3 } } */ /* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.d} 3 } } */ -/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.s} 3 } } */ -/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cune\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cune\.d} 3 } } */ /* { dg-final { scan-assembler-times {\txvfcmp\.slt\.s} 6 } } */ /* { dg-final { scan-assembler-times {\txvfcmp\.slt\.d} 6 } } */ /* { dg-final { scan-assembler-times {\txvfcmp\.sle\.s} 6 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c index 2214afd0a89..486bedba430 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c @@ -69,8 +69,8 @@ TEST_CMP (nugt) /* { dg-final { scan-assembler-times {\tvfcmp\.ceq\.s} 3 } } */ /* { dg-final { scan-assembler-times {\tvfcmp\.ceq\.d} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcmp\.cne\.s} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcmp\.cne\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cune\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cune\.d} 3 } } */ /* { dg-final { scan-assembler-times {\tvfcmp\.slt\.s} 6 } } */ /* { dg-final { scan-assembler-times {\tvfcmp\.slt\.d} 6 } } */ /* { dg-final { scan-assembler-times {\tvfcmp\.sle\.s} 6 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c b/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c new file mode 100644 index 00000000000..8b870ef38a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ + +#define F double +#define I long long + +#include "vfcmp-f.c" + +/* { dg-final { scan-assembler "compare_quiet_equal:.*\tvfcmp\\.ceq\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\tvfcmp\\.cune\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater:.*\tvfcmp\\.slt\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\tvfcmp\\.sle\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less:.*\tvfcmp\\.slt\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\tvfcmp\\.sle\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\tvfcmp\\.sule\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\tvfcmp\\.sult\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_less:.*\tvfcmp\\.sule\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\tvfcmp\\.sult\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less:.*\tvfcmp\\.clt\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\tvfcmp\\.cle\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater:.*\tvfcmp\\.clt\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\tvfcmp\\.cle\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_less:.*\tvfcmp\\.cule\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\tvfcmp\\.cult\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\tvfcmp\\.cule\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\tvfcmp\\.cult\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_unordered:.*\tvfcmp\\.cun\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_ordered:.*\tvfcmp\\.cor\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_ordered\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c b/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c new file mode 100644 index 00000000000..b9110b90cb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c @@ -0,0 +1,178 @@ +/* Test mapping IEC 60559 operations to SIMD instructions. + For details read C23 Annex F.3 and LoongArch Vol. 1 section 3.2.2.1. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ + +#ifndef F +#define F float +#endif + +#ifndef I +#define I int +#endif + +#ifndef VL +#define VL 16 +#endif + +typedef F VF __attribute__ ((vector_size (VL))); +typedef I VI __attribute__ ((vector_size (VL))); + +register VF a asm ("f0"); +register VF b asm ("f1"); +register VI c asm ("f2"); + +void +compare_quiet_equal (void) +{ + c = (a == b); +} + +void +compare_quiet_not_equal (void) +{ + c = (a != b); +} + +void +compare_signaling_greater (void) +{ + c = (a > b); +} + +void +compare_signaling_greater_equal (void) +{ + c = (a >= b); +} + +void +compare_signaling_less (void) +{ + c = (a < b); +} + +void +compare_signaling_less_equal (void) +{ + c = (a <= b); +} + +void +compare_signaling_not_greater (void) +{ + c = ~(a > b); +} + +void +compare_signaling_less_unordered (void) +{ + c = ~(a >= b); +} + +void +compare_signaling_not_less (void) +{ + c = ~(a < b); +} + +void +compare_signaling_greater_unordered (void) +{ + c = ~(a <= b); +} + +void +compare_quiet_less (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isless (a[i], b[i]) ? -1 : 0; +} + +void +compare_quiet_less_equal (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_islessequal (a[i], b[i]) ? -1 : 0; +} + +void +compare_quiet_greater (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isgreater (a[i], b[i]) ? -1 : 0; +} + +void +compare_quiet_greater_equal (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isgreaterequal (a[i], b[i]) ? -1 : 0; +} + +void +compare_quiet_not_less (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isless (a[i], b[i]) ? 0 : -1; +} + +void +compare_quiet_greater_unordered (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_islessequal (a[i], b[i]) ? 0 : -1; +} + +void +compare_quiet_not_greater (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isgreater (a[i], b[i]) ? 0 : -1; +} + +void +compare_quiet_less_unordered (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isgreaterequal (a[i], b[i]) ? 0 : -1; +} + +void +compare_quiet_unordered (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isunordered (a[i], b[i]) ? -1 : 0; +} + +void +compare_quiet_ordered (void) +{ + for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) + c[i] = __builtin_isunordered (a[i], b[i]) ? 0 : -1; +} + +/* The "-" matches the .size directive after the function + body, so we can ensure the instruction is in the correct function. */ + +/* { dg-final { scan-assembler "compare_quiet_equal:.*\tvfcmp\\.ceq\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\tvfcmp\\.cune\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater:.*\tvfcmp\\.slt\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\tvfcmp\\.sle\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less:.*\tvfcmp\\.slt\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\tvfcmp\\.sle\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\tvfcmp\\.sule\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\tvfcmp\\.sult\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_less:.*\tvfcmp\\.sule\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\tvfcmp\\.sult\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less:.*\tvfcmp\\.clt\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\tvfcmp\\.cle\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater:.*\tvfcmp\\.clt\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\tvfcmp\\.cle\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_less:.*\tvfcmp\\.cule\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\tvfcmp\\.cult\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\tvfcmp\\.cule\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\tvfcmp\\.cult\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_unordered:.*\tvfcmp\\.cun\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_ordered:.*\tvfcmp\\.cor\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_ordered\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c b/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c new file mode 100644 index 00000000000..d8017caaa01 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ + +#define F double +#define I long long +#define VL 32 + +#include "vfcmp-f.c" + +/* { dg-final { scan-assembler "compare_quiet_equal:.*\txvfcmp\\.ceq\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\txvfcmp\\.cune\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater:.*\txvfcmp\\.slt\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\txvfcmp\\.sle\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less:.*\txvfcmp\\.slt\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\txvfcmp\\.sle\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\txvfcmp\\.sule\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\txvfcmp\\.sult\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_less:.*\txvfcmp\\.sule\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\txvfcmp\\.sult\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less:.*\txvfcmp\\.clt\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\txvfcmp\\.cle\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater:.*\txvfcmp\\.clt\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\txvfcmp\\.cle\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_less:.*\txvfcmp\\.cule\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\txvfcmp\\.cult\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\txvfcmp\\.cule\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\txvfcmp\\.cult\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_unordered:.*\txvfcmp\\.cun\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_ordered:.*\txvfcmp\\.cor\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_ordered\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c b/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c new file mode 100644 index 00000000000..b5455647554 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -ffixed-f0 -ffixed-f1 -ffixed-f2" } */ + +#define VL 32 + +#include "vfcmp-f.c" + +/* { dg-final { scan-assembler "compare_quiet_equal:.*\txvfcmp\\.ceq\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\txvfcmp\\.cune\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater:.*\txvfcmp\\.slt\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\txvfcmp\\.sle\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less:.*\txvfcmp\\.slt\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\txvfcmp\\.sle\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\txvfcmp\\.sule\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\txvfcmp\\.sult\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_not_less:.*\txvfcmp\\.sule\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\txvfcmp\\.sult\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less:.*\txvfcmp\\.clt\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\txvfcmp\\.cle\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater:.*\txvfcmp\\.clt\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\txvfcmp\\.cle\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_equal\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_less:.*\txvfcmp\\.cule\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_not_less\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\txvfcmp\\.cult\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\txvfcmp\\.cule\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_greater\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\txvfcmp\\.cult\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_unordered:.*\txvfcmp\\.cun\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_unordered\n" } } */ +/* { dg-final { scan-assembler "compare_quiet_ordered:.*\txvfcmp\\.cor\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_ordered\n" } } */