From patchwork Wed Dec 13 03:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 82020 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8541E3858019 for ; Wed, 13 Dec 2023 03:26:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by sourceware.org (Postfix) with ESMTP id C030A3858C2F for ; Wed, 13 Dec 2023 03:25:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C030A3858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C030A3858C2F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=206.189.21.223 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702437954; cv=none; b=BFiJY89dSQIMMv6xG7yPVpGgSWMRxgWrDEX4KJ0BVge/EO9ngecgbqYa5IdoiPim1QlPi+rqExYI8s0Qh/rbSoZP7dOw/N+q7q/ZsZNBq+ZXR5Htut9YljLcmkUKOSG4SZ2Tmsekxaiwkagi2HtG444jMKop8AzaHJj+9IeR8Tg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702437954; c=relaxed/simple; bh=JMa1m6JvSGFA1d22KbOCNbwJOqtxdTlGrfbutImRbYc=; h=From:To:Subject:Date:Message-Id; b=E/wbehtP1oXnWlbptKv3ohqJNNCRuQ3owz7823sBeYOiMEJAOyFmOXyTWJsqTN2Yq+HM8V/OPCE5PPUyraTTFNHo6sIKUh1HdEdTedor1cLEYe0rfRKA2rH9qXyb5JTDVcK1+MJ4CZPCjYnoC25JziMeosjLC/B9vGyH3/AoNUY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgAXlvvtI3llsD4BAA--.6373S4; Wed, 13 Dec 2023 11:24:30 +0800 (CST) From: Xiao Zeng To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, research_trasio@irq.a4lg.com, kito.cheng@gmail.com, pan2.li@intel.com, Xiao Zeng Subject: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option Date: Wed, 13 Dec 2023 11:24:51 +0800 Message-Id: <20231213032451.8054-1-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgAXlvvtI3llsD4BAA--.6373S4 X-Coremail-Antispam: 1UD129KBjvJXoW3Jr13GF1kJrW5Kr4kAw4UCFg_yoWxZw4DpF 4rG39YkrWrXF9rWayfJa48Zw43AanYgrW5Cws7u347Aw43JrWxJF1kK3Wavr98XF4rurya k3WI9r1Yvw1UW37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch would like to add new sub extension (aka Zvfbfmin) to the -march= option. It introduces a new data type BF16. Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. You can locate more information about Zvfbfmin from below spec doc. https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfbfmin item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt: (MASK_ZVFBFMIN): New macro. (MASK_VECTOR_ELEN_BF_16): Ditto. (TARGET_ZVFBFMIN): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-31.c: New test. * gcc.target/riscv/arch-32.c: New test. * gcc.target/riscv/predef-32.c: New test. * gcc.target/riscv/predef-33.c: New test. Reviewed-by: Palmer Dabbelt --- gcc/common/config/riscv/riscv-common.cc | 4 ++ gcc/config/riscv/riscv.opt | 4 ++ gcc/testsuite/gcc.target/riscv/arch-31.c | 5 +++ gcc/testsuite/gcc.target/riscv/arch-32.c | 5 +++ gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++++++++++++++++++++++ 6 files changed, 104 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4d5a2f874a2..370d00b8f7a 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfa", "f"}, + {"zvfbfmin", "zve32f"}, {"zvfhmin", "zve32f"}, {"zvfh", "zve32f"}, {"zvfh", "zfhmin"}, @@ -313,6 +314,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, + {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, {"zvfh", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, @@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, + {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 59ce7106ecf..b7c0b72265e 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -285,6 +285,8 @@ Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags) Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags) +Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags) + TargetVariable int riscv_zvl_flags @@ -366,6 +368,8 @@ Mask(ZFHMIN) Var(riscv_zf_subext) Mask(ZFH) Var(riscv_zf_subext) +Mask(ZVFBFMIN) Var(riscv_zf_subext) + Mask(ZVFHMIN) Var(riscv_zf_subext) Mask(ZVFH) Var(riscv_zf_subext) diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c new file mode 100644 index 00000000000..5180753b905 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c new file mode 100644 index 00000000000..49616832512 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c b/gcc/testsuite/gcc.target/riscv/predef-32.c new file mode 100644 index 00000000000..7417e0d996f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 32 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zvfbfmin) +#error "__riscv_zvfbfmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c b/gcc/testsuite/gcc.target/riscv/predef-33.c new file mode 100644 index 00000000000..74d05bc9719 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_d) +#error "__riscv_d" +#endif + +#if !defined(__riscv_v) +#error "__riscv_v" +#endif + +#if !defined(__riscv_zvfbfmin) +#error "__riscv_zvfbfmin" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +}