From patchwork Tue Dec 12 19:32:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mary Bennett X-Patchwork-Id: 82001 X-Patchwork-Delegate: kito.cheng@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D71FC385C405 for ; Tue, 12 Dec 2023 19:33:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id AE4AF3858C2F for ; Tue, 12 Dec 2023 19:33:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AE4AF3858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AE4AF3858C2F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::32a ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702409598; cv=none; b=DPYpcMycauiHd63X+UYWkwnNnHlBHjv2HGSJ+TL4C6zFHzxgSmv9SsyPikfHWlO7vFwSg3fqPXHD6bCXjBl5/uGH0QvayYp+pUbhanYmqRzonzskqjjLu2A+9S4qorK0UNnndE1dqOmBnK8ILztqtaGZgByvpFqlZkpkLJl7Q9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702409598; c=relaxed/simple; bh=kLW5gvZR7/Xvn0pqoT6ymTy0Y1sNe9eI537hSe36nOI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=vq9/e1jafzTqq0EN4ZK70x3gaonGSSf5MIhQxPQ3cXj9P2fOFh5pOrEsShKCli7zwzJECudcxmME0di1pBy+uvkAhWqA4uVJTVfgEPUdnnKJnYTfswrgi5skPI30BdM03t7XnqZM152IM0f8p08Te5MZe4hc8O//eN1+vwiZ+DU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40c29f7b068so57400905e9.0 for ; Tue, 12 Dec 2023 11:33:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1702409595; x=1703014395; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sSuHUA4mdFmIgo7RQ/etAxazrYatB6vswvSr2C5WUpI=; b=JdhhE2w4eS+upiqGruALS/bqP+tJ13QVLopSX9zEcLvfGGzNcf9LGgpA1BEmRBGEpK D1jfPGR6V86Cys0DdcxYYHEZ93TbDhOVME2NXIHrXMLQgxLLj7xOZ5l9IeOPqjbUCHxy JbQaXnwHqjvVMKgTzB5LjOhRafFDrIsxHPoACoD5zzj1mhiOxferjCukd2fHyM1V6N16 hW6YXNcVcs3Gd3FHddQhYvqE2chfeC/CnUJ5cpT3ncy5AgVe6OG4nP8RlC3KkwadUZpG 56l0+B4deaI4BmGRUGEdY40wDuQp5YbMWX0gFNjovdd0dtGJYRSqRzrITCfrJQ3pfAxg eddg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702409595; x=1703014395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sSuHUA4mdFmIgo7RQ/etAxazrYatB6vswvSr2C5WUpI=; b=GO4BHsz+STiBlt3UPnuxmzuiGE/8DsFsOMQEFANH1hujdukw3x67Pqj0yKnp8UrVqi /TT9uPB+yblG60B/b5jKNDHMttPH2+ftL2hAYRlQVjKz+VP7W1T+2joLtXOsBSVbNpUV FaqKff4pLJhB0EIVtVbE18Q9yjj8jnvI4pYmZ/ttWQkUkbJePbjH/URgoww6xcQudU2w gEKBElhPWMJ3U9yw510LYe4g3In2GvDlv0aymw6O8yBxAHhnMVdwjQrJbHSNup6ppAFP f6aXYBrRr9GEjjSfAG5ggf0F5mRcWCags74rTL1JW3+9z7db+uRxwEBXG9VCcm8VzhRR gfjQ== X-Gm-Message-State: AOJu0Yy3RFz5c+wejxVrc733k+B1Sxfhk1T3QCKyR0CPtm7o5k/QzP7+ s3skkacHoWRBFqC5afkg8Uc61QhrNVV9ZMOWzgg= X-Google-Smtp-Source: AGHT+IGZc74ja7x1/gU7bvp3gsqldcyxoOqO0InR/umar/If/DA1pTFN51O4qWjLyvakh9eXhGt0gw== X-Received: by 2002:a05:600c:314f:b0:40c:467a:6a5a with SMTP id h15-20020a05600c314f00b0040c467a6a5amr2016201wmo.122.1702409594737; Tue, 12 Dec 2023 11:33:14 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm19934150wmb.27.2023.12.12.11.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 11:33:14 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Date: Tue, 12 Dec 2023 19:32:51 +0000 Message-Id: <20231212193253.220195-2-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212193253.220195-1-mary.bennett@embecosm.com> References: <20231128131615.3986922-1-mary.bennett@embecosm.com> <20231212193253.220195-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVelw. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVelw builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw. * testsuite/lib/target-supports.exp: Add proc for the XCVelw extension. --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/corev.def | 3 +++ gcc/config/riscv/corev.md | 15 +++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 2 ++ gcc/config/riscv/riscv-ftypes.def | 1 + gcc/config/riscv/riscv.opt | 2 ++ gcc/doc/extend.texi | 8 ++++++++ gcc/doc/sourcebuild.texi | 3 +++ .../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++ gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++ 10 files changed, 60 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 5111626157b..c8c0d0a2252 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, + {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def index 17580df3c41..3b9ec029d06 100644 --- a/gcc/config/riscv/corev.def +++ b/gcc/config/riscv/corev.def @@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu), RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu), RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu), + +// XCVELW +RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw), diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index 1350bd4b81e..c7a2ba07bcc 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -24,6 +24,9 @@ UNSPEC_CV_ALU_CLIPR UNSPEC_CV_ALU_CLIPU UNSPEC_CV_ALU_CLIPUR + + ;;CORE-V EVENT LOAD + UNSPECV_CV_ELW ]) ;; XCVMAC extension. @@ -691,3 +694,15 @@ cv.suburnr\t%0,%2,%3" [(set_attr "type" "arith") (set_attr "mode" "SI")]) + +;; XCVELW builtins +(define_insn "riscv_cv_elw_elw_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(match_operand:SI 1 "move_operand" "p")] + UNSPECV_CV_ELW))] + + "TARGET_XCVELW && !TARGET_64BIT" + "cv.elw\t%0,%a1" + + [(set_attr "type" "load") + (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index fc3976f3ba1..5ee11ebe3bc 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0)) // CORE-V AVAIL AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) +AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. @@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) #define RISCV_ATYPE_HI intHI_type_node #define RISCV_ATYPE_SI intSI_type_node #define RISCV_ATYPE_VOID_PTR ptr_type_node +#define RISCV_ATYPE_INT_PTR integer_ptr_type_node /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists their associated RISCV_ATYPEs. */ diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 0d1e4dd061e..3e7d5c69503 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI)) DEF_RISCV_FTYPE (0, (VOID)) DEF_RISCV_FTYPE (1, (VOID, USI)) DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) +DEF_RISCV_FTYPE (1, (USI, VOID_PTR)) DEF_RISCV_FTYPE (1, (USI, USI)) DEF_RISCV_FTYPE (1, (UDI, UDI)) DEF_RISCV_FTYPE (1, (USI, UQI)) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 11526f9cc2a..bfa0945daca 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext) Mask(XCVALU) Var(riscv_xcv_subext) +Mask(XCVELW) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 9474e9398bb..b89aa915b7e 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22084,6 +22084,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in Generated assembler @code{cv.subuRNr} if the it is a register. @end deftypefn +These built-in functions are available for the CORE-V Event Load machine +architecture. For more information on CORE-V ELW builtins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw} + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *) +Generated assembler @code{cv.elw} +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index e27e0fa606c..d63b11d245c 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension. @item cv_alu Test system has support for the CORE-V ALU extension. +@item cv_elw +Test system has support for the CORE-V ELW extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c new file mode 100644 index 00000000000..30f951c3f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_elw } */ +/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */ + +int +foo (void* b) +{ + return __builtin_riscv_cv_elw_elw (b + 8); +} + +/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 87b2ae58720..c324a7898fc 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13147,6 +13147,19 @@ proc check_effective_target_cv_alu { } { } "-march=rv32i_xcvalu" ] } +# Return 1 if the CORE-V ELW extension is available. +proc check_effective_target_cv_elw { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_elw object { + void foo (void) + { + asm ("cv.elw x0, 0(x0)"); + } + } "-march=rv32i_xcvelw" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx)