From patchwork Mon Dec 11 12:20:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 81899 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 638883858D37 for ; Mon, 11 Dec 2023 12:22:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by sourceware.org (Postfix) with ESMTPS id 238C23858D37 for ; Mon, 11 Dec 2023 12:22:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 238C23858D37 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 238C23858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702297347; cv=none; b=kQrUyW3nEf4XeIBSCS6CzPDnFYOecZMgepD6HN7anleMXSRjxGzIpsletZ+4u5bn3yEPRFZQ2ZDAg++EqSeQ8SmY9BfDvBwOo+yzsn28uR9iMNa2Uzg7HRRerGNyZ3Q9c/NybbIIh6ySLOB93Z41RmorWxm6paxyL9uoxd9BLMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702297347; c=relaxed/simple; bh=PLNZkIJUYtKJNwdI5u61sr5hl/1i1VdKH9OiHmMukAs=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=H2He3FtLfRZEAAXxFqS7P1zQNF60rwUXB8MEC1PC3/07Ib9Nl5iBvx/NtFbolmAs89G71L4QUl0vSnbsvqUUXmiyGFLnYdIs9O63eCNieLBtky9X0/4zxlPB3eu6z4xinCyBVspwZ4tSnLmIW+i3+b48jTPpnV+/onCflaPOJ6w= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702297345; x=1733833345; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PLNZkIJUYtKJNwdI5u61sr5hl/1i1VdKH9OiHmMukAs=; b=bV6RouIYRKb/otNyLSmPoJtheQLCi45yJ6mUzcM3cV9518iSbyKgZcCJ yNgaMyT1ByBm/btzaOVv0qvEiQH8s41PhqWCUhlNiLH90ooHD6tDKU17G x/fut63WDmDYSW7nlPE6EiBYkMejBtPW7Ri86k0vTUtMOKq+zD/hMULXG mFH2Xoq9CYl9FaXo0Z7g+rOeFIp+vq1eKiWrmP8cwH1No7jqdEGe8YXgI 30zgcaO674emlim3Rx/fAMKY9YGxpqRw1AOpdoNAXDJt4Lfvs9+V/JyG/ mhdC2N85wEOlVNJ5YtLElyClnjA7N26MGS7nfAOEiYPQAcCI869fwLE45 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10920"; a="1509899" X-IronPort-AV: E=Sophos;i="6.04,267,1695711600"; d="scan'208";a="1509899" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2023 04:22:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10920"; a="776657754" X-IronPort-AV: E=Sophos;i="6.04,267,1695711600"; d="scan'208";a="776657754" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 11 Dec 2023 04:22:21 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 05B541005682; Mon, 11 Dec 2023 20:22:21 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943] Date: Mon, 11 Dec 2023 20:20:20 +0800 Message-Id: <20231211122020.3645581-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi, The ashl/lshr/ashr expanders calls ix86_expand_binary_operator, while they will be called for some post-reload split, and TARGET_APX_NDD is required for these calls to avoid force-load to memory at postreload stage. Bootstrapped/regtested on x86-64-pc-linux-gnu{-m32,} Ok for master? gcc/ChangeLog: PR target/112943 * config/i386/i386.md (ashl3): Add TARGET_APX_NDD to ix86_expand_binary_operator call. (3): Likewise for rshift. (di3): Likewise for DImode rotate. (3): Likewise for SWI124 rotate. gcc/testsuite/ChangeLog: PR target/112943 * gcc.target/i386/pr112943.c: New test. --- gcc/config/i386/i386.md | 12 +++-- gcc/testsuite/gcc.target/i386/pr112943.c | 63 ++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr112943.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b4db50f61cd..f83064ec335 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14308,7 +14308,8 @@ (define_expand "ashl3" (ashift:SDWIM (match_operand:SDWIM 1 "") (match_operand:QI 2 "nonmemory_operand")))] "" - "ix86_expand_binary_operator (ASHIFT, mode, operands); DONE;") + "ix86_expand_binary_operator (ASHIFT, mode, operands, + TARGET_APX_NDD); DONE;") (define_insn_and_split "*ashl3_doubleword_mask" [(set (match_operand: 0 "register_operand") @@ -15564,7 +15565,8 @@ (define_expand "3" (any_shiftrt:SDWIM (match_operand:SDWIM 1 "") (match_operand:QI 2 "nonmemory_operand")))] "" - "ix86_expand_binary_operator (, mode, operands); DONE;") + "ix86_expand_binary_operator (, mode, operands, + TARGET_APX_NDD); DONE;") ;; Avoid useless masking of count operand. (define_insn_and_split "*3_mask" @@ -16791,7 +16793,8 @@ (define_expand "di3" "" { if (TARGET_64BIT) - ix86_expand_binary_operator (, DImode, operands); + ix86_expand_binary_operator (, DImode, operands, + TARGET_APX_NDD); else if (const_1_to_31_operand (operands[2], VOIDmode)) emit_insn (gen_ix86_di3_doubleword (operands[0], operands[1], operands[2])); @@ -16811,7 +16814,8 @@ (define_expand "3" (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") (match_operand:QI 2 "nonmemory_operand")))] "" - "ix86_expand_binary_operator (, mode, operands); DONE;") + "ix86_expand_binary_operator (, mode, operands, + TARGET_APX_NDD); DONE;") ;; Avoid useless masking of count operand. (define_insn_and_split "*3_mask" diff --git a/gcc/testsuite/gcc.target/i386/pr112943.c b/gcc/testsuite/gcc.target/i386/pr112943.c new file mode 100644 index 00000000000..45da6cce5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112943.c @@ -0,0 +1,63 @@ +/* PR target/112943 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=westmere -mapxf" } */ + +typedef unsigned char __attribute__((__vector_size__(1))) v8u8; +typedef char __attribute__((__vector_size__(2))) v16u8; +typedef char __attribute__((__vector_size__(4))) v32u8; +typedef char __attribute__((__vector_size__(8))) v64u8; +typedef char __attribute__((__vector_size__(16))) v128u8; +typedef _Float16 __attribute__((__vector_size__(2))) v16f16; +typedef _Float16 __attribute__((__vector_size__(16))) v128f16; +typedef _Float64x __attribute__((__vector_size__(16))) v128f128; +typedef _Decimal64 d64; +char foo0_u8_0; +v8u8 foo0_v8u8_0; +__attribute__((__vector_size__(sizeof(char)))) char foo0_v8s8_0; +__attribute__((__vector_size__(sizeof(long)))) unsigned long v64u64_0; +_Float16 foo0_f16_0; +v128f16 foo0_v128f16_0; +double foo0_f64_0; +int foo0_f128_0, foo0_v32d32_0, foo0__0; +d64 foo0_d64_0; +v8u8 *foo0_ret; +unsigned __int128 foo0_u128_3; +v8u8 d; +void foo0() { + v64u64_0 -= foo0_u8_0; + v8u8 v8u8_1 = foo0_v8u8_0 % d; + v128f128 v128f128_1 = __builtin_convertvector(v64u64_0, v128f128); + __int128 u128_2 = (9223372036854775808 << 4) * foo0_u8_0; /* { dg-warning "integer constant is so large that it is unsigned" "so large" } */ + __int128 u128_r = u128_2 + foo0_u128_3 + foo0_f128_0 + (__int128)foo0_d64_0; + v16f16 v16f16_1 = __builtin_convertvector(foo0_v8s8_0, v16f16); + v128f16 v128f16_1 = 0 > foo0_v128f16_0; + v128u8 v128u8_r = (v128u8)v128f16_1 + (v128u8)v128f128_1; + v64u8 v64u8_r = ((union { + v128u8 a; + v64u8 b; + })v128u8_r) + .b + + (v64u8)v64u64_0; + v32u8 v32u8_r = ((union { + v64u8 a; + v32u8 b; + })v64u8_r) + .b + + (v32u8)foo0_v32d32_0; + v16u8 v16u8_r = ((union { + v32u8 a; + v16u8 b; + })v32u8_r) + .b + + (v16u8)v16f16_1; + v8u8 v8u8_r = ((union { + v16u8 a; + v8u8 b; + })v16u8_r) + .b + + foo0_v8u8_0 + v8u8_1 + foo0_v8s8_0; + long u64_r = u128_r + foo0_f64_0 + (unsigned long)foo0__0; + short u16_r = u64_r + foo0_f16_0; + char u8_r = u16_r + foo0_u8_0; + *foo0_ret = v8u8_r + u8_r; +}