From patchwork Tue Dec 5 06:44:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 81337 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9DD5938768B8 for ; Tue, 5 Dec 2023 06:45:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id E40093857C61 for ; Tue, 5 Dec 2023 06:45:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E40093857C61 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E40093857C61 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701758723; cv=none; b=S98yXnWvE2gP9tGSaXtmhhjohUJYNF/hLaGupPci+b44n3X9KSmpMNCJiZBLESNUPrVr1QzVuAFKgJ0yM7b8pD0sem8csONhikYdn5nNU8DLGuaegkbMqrXvYNCFeUAX9b7jeyp4scEwxqJvCPUxbu1dqrY9JPRrAg7Zkd72lFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701758723; c=relaxed/simple; bh=Uz0UKhRudsfYfo6tRqk0IaYZ48Hgg7WP/voeCKgSf6k=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=m3ViTyi2E5bu6DH1LW0Dond15pHIoT9DGTFDSAG+RzW1q6Cc076NZYQGp5wSFDGwK8TFdkv/NIeSWmFPQHNfFrIwMF2WPMN9k2cuRxfClVLsmTn4bycqcEHveElCdwBni9v7LLVwqg6HYMQxiF/JgRNtwNwbCOFvPsA3G0i1DHY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rAPB6-0008Cn-4C for gcc-patches@gcc.gnu.org; Tue, 05 Dec 2023 01:45:11 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8DxPOvnxm5lNPg+AA--.54566S3; Tue, 05 Dec 2023 14:44:56 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxfS_lxm5l+zVVAA--.57439S4; Tue, 05 Dec 2023 14:44:53 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, chenxiaolong Subject: [PATCH v2] LoongArch: Add asm modifiers to the LSX and LASX directives in the doc. Date: Tue, 5 Dec 2023 14:44:35 +0800 Message-Id: <20231205064435.61292-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxfS_lxm5l+zVVAA--.57439S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAPBWVtNywHRgAFsc X-Coremail-Antispam: 1Uk129KBj93XoWxWFWftrykGrWkArWkKFyxXrc_yoW5Ary5pw srCwnYgrn7Gan29w1fAw48uFn8J392y3yUCrW7tryqkwn0gry0qr43tFy293s7Ca1YvrW7 t3yUJ3y8Ca4YyagCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jUsqXUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * doc/extend.texi:Add modifiers to the vector of asm in the doc. * doc/md.texi:Refine the description of the modifier 'f' in the doc. --- gcc/doc/extend.texi | 47 +++++++++++++++++++++++++++++++++++++++++++++ gcc/doc/md.texi | 2 +- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 32ae15e1d5b..d87a079704c 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -11820,10 +11820,57 @@ The list below describes the supported modifiers and their effects for LoongArch @item @code{d} @tab Same as @code{c}. @item @code{i} @tab Print the character ''@code{i}'' if the operand is not a register. @item @code{m} @tab Same as @code{c}, but the printed value is @code{operand - 1}. +@item @code{u} @tab Print a LASX register. +@item @code{w} @tab Print a LSX register. @item @code{X} @tab Print a constant integer operand in hexadecimal. @item @code{z} @tab Print the operand in its unmodified form, followed by a comma. @end multitable +References to input and output operands in the assembler template of extended +asm statements can use modifiers to affect the way the operands are formatted +in the code output to the assembler. For example, the following code uses the +'w' modifier for LoongArch: + +@example +test-asm.c: + +#include + +__m128i foo (void) +@{ +__m128i a,b,c; +__asm__ ("vadd.d %w0,%w1,%w2\n\t" + :"=f" (c) + :"f" (a),"f" (b)); + +return c; +@} + +@end example + +@noindent +The compile command for the test case is as follows: + +@example +gcc test-asm.c -mlsx -S -o test-asm.s +@end example + +@noindent +The assembly statement produces the following assembly code: + +@example +vadd.d $vr0,$vr0,$vr1 +@end example + +This is a 128-bit vector addition instruction, @code{c} (referred to in the +template string as %0) is the output, and @code{a} (%1) and @code{b} (%2) are +the inputs. @code{__m128i} is a vector data type defined in the file +@code{lsxintrin.h} (@xref{LoongArch SX Vector Intrinsics}). The symbol '=f' +represents a constraint using a floating-point register as an output type, and +the 'f' in the input operand represents a constraint using a floating-point +register operand, which can refer to the definition of a constraint +(@xref{Constraints}) in gcc. + @anchor{riscvOperandmodifiers} @subsubsection RISC-V Operand Modifiers diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 536ce997f01..2274da5ff69 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2881,7 +2881,7 @@ $r1h @item LoongArch---@file{config/loongarch/constraints.md} @table @code @item f -A floating-point register (if available). +A floating-point or vector register (if available). @item k A memory operand whose address is formed by a base register and (optionally scaled) index register.