From patchwork Tue Dec 5 03:22:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juzhe-Zhong X-Patchwork-Id: 81329 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE1C8382B32F for ; Tue, 5 Dec 2023 03:23:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id B9586388E4A5 for ; Tue, 5 Dec 2023 03:23:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B9586388E4A5 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B9586388E4A5 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701746609; cv=none; b=Brj3E/OQjXj940Dnuw2DnuUrE7R40H2Rowz4iwacJKiW0/1Gj1IINuhi98kPDaxUqyFwNHTHFg/OdD0Bp5f0bCxMJD0ya7+vPnK6r3gRi5tWWBnTePR7D6MDuYxM8yKCNYPSfAJN8hgJUtdeP1vf0galKSEWAoTPbTVE1mR3cp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701746609; c=relaxed/simple; bh=mpcx5AwdHLJHuDJ6U9/zunLy2DWPpT/UldtT8LxYuPU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=va8QNPja6tsJTxvK3mFkwBIGj+MaPLtfk+Mzt9MTiij+E+3tzQRsNObHp9K12b9Uu4Xre+h/bqxbsZqu74uiP4nxJsj+eUIJFW8HDnSX/OOEziWMu9ibLxsGkEVmovI4dun/xWVOAp7GKiLAWwt5RFhOxNTbVZ/mlgA04hWRjdw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp71t1701746572t8ir5e5c Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 05 Dec 2023 11:22:51 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: aBJFcW+uBGZQsbus/Sawv4/SP1hOAdFjtOWABeruD4qr0tnqJCVILCmTvncW5 IMNDClImkDOzlQ0iKYWkQghprsYq4fBMW7+xoF6KQdMeRBTXHo5roC70TD0VBcmqM3MD2UU a2xMXJLsvAUy0NstttnnV3oPTRhx+FeiarxCkJ39baIaZkFJE8RxQ+nTVOLkiHu6odPkHHj xRdG+rZuuQkbCT8EN8fm2v589L1RiIWh/zd60uuY2TCQpmZXdrby9xfRtKg78SUNOM+coPR csDiypAO8G/nnqySdLaUoOkJziKtbg3v0sSlLgg8SjAtZlvVVC3EIaaWte5sxahq1MofiaJ hP3hNiycPuKc5ZMQM1cNi0KpaefzhMtcaGrNNWhuTHiMLZEHggFIo43GM+y8IpPOpyFPfWi AuJzaabh2mY= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4800353167631992775 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add blocker for gather/scatter auto-vectorization Date: Tue, 5 Dec 2023 11:22:50 +0800 Message-Id: <20231205032250.1270125-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch fixes ICE exposed on full coverage testing: === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=dynamic === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=m4 === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=m8 === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) === g++: Unexpected fails for rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax === FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++17 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++20 (internal compiler error: in require, at machmode.h:313) FAIL: g++.dg/pr106219.C -std=gnu++98 (internal compiler error: in require, at machmode.h:313) The rootcause is we can't extend RVVM4SImode into RVVM8DImode on zve32f. Add a blocker of it to disable such auto-vectorization in this situation. gcc/ChangeLog: * config/riscv/autovec.md: Add blocker. * config/riscv/riscv-protos.h (gather_scatter_valid_offset_p): New function. * config/riscv/riscv-v.cc (gather_scatter_valid_offset_p): Ditto. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/autovec/bug-2.C: New test. --- gcc/config/riscv/autovec.md | 24 ++++++++--------- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 18 +++++++++++++ .../g++.target/riscv/rvv/autovec/bug-2.C | 26 +++++++++++++++++++ 4 files changed, 57 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 2d727c2609b..b9f7aa204da 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -59,7 +59,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -74,7 +74,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -89,7 +89,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -104,7 +104,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -119,7 +119,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -134,7 +134,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, true); DONE; @@ -172,7 +172,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; @@ -187,7 +187,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; @@ -202,7 +202,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; @@ -217,7 +217,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; @@ -232,7 +232,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; @@ -247,7 +247,7 @@ (match_operand: 5 "vector_mask_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_p (mode)" { riscv_vector::expand_gather_scatter (operands, false); DONE; diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 695ee24ad6f..bfbd2bf0d18 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -606,6 +606,7 @@ enum vlmul_type get_vlmul (rtx_insn *); int count_regno_occurrences (rtx_insn *, unsigned int); bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); +bool gather_scatter_valid_offset_p (machine_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 588c127343e..dd659f99f91 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4686,4 +4686,22 @@ emit_vec_extract (rtx target, rtx src, poly_int64 index) emit_move_insn (target, ops[0].value); } +/* Return true if the offset mode is valid mode that we use for gather/scatter + autovectorization. */ +bool +gather_scatter_valid_offset_p (machine_mode mode) +{ + /* If the element size of offset mode is already >= Pmode size, + we don't need any extensions. */ + if (known_ge (GET_MODE_SIZE (GET_MODE_INNER (mode)), UNITS_PER_WORD)) + return true; + + /* Since we are very likely extend the offset mode into vector Pmode, + Disable gather/scatter autovectorization if we can't extend the offset + mode into vector Pmode. */ + if (!get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists ()) + return false; + return true; +} + } // namespace riscv_vector diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C new file mode 100644 index 00000000000..53bc4a30072 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C @@ -0,0 +1,26 @@ +/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4" } */ + +int max(int __b) { + if (0 < __b) + return __b; + return 0; +} +struct Plane { + Plane(int, int); + int *Row(); +}; +float *ConvolveXSampleAndTranspose_rowp; +int ConvolveXSampleAndTranspose_res, ConvolveXSampleAndTranspose_r; +void ConvolveXSampleAndTranspose() { + Plane out(0, ConvolveXSampleAndTranspose_res); + for (int y;;) { + float sum; + for (int i = ConvolveXSampleAndTranspose_r; i; ++i) + sum += i; + for (; ConvolveXSampleAndTranspose_r; ++ConvolveXSampleAndTranspose_r) + sum += + ConvolveXSampleAndTranspose_rowp[max(ConvolveXSampleAndTranspose_r)] * + ConvolveXSampleAndTranspose_r; + out.Row()[y] = sum; + } +}