From patchwork Tue Dec 5 02:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 81310 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AF54F3954C6E for ; Tue, 5 Dec 2023 02:31:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 56788386CE56 for ; Tue, 5 Dec 2023 02:30:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 56788386CE56 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 56788386CE56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701743452; cv=none; b=TDVX9oql+aE1JCz93xIJ4hFTUvaZqamiMN5LIKh/SZ6vDF0eHD8GYb/utH2lJPwz4A/ypJViLrC2vAOuqyVGQnl0IyeEhOwFXj0WVkXfLwhlOWgHTw6wvzzAtt/qNhvdducd+crkUycUILrn1M4zrUXW1HquqVsx30fEPnOQ94w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701743452; c=relaxed/simple; bh=XRBPWrpdm8I3QTJ9VGy/xsLqvBl4DFS5mO/9mz4pfaU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=YIJxafXTR4bzglKJzJNF8W/rUFk1GR0eqEumbPzz7dBOpV2m8jHieGMWPwy1icT6AmPTKop9D6SLn1Ju23UL/Kx6X2cYfuwCa6ZhmaI0Gnt5yDIfXuz3p9hhsCtHFGyolPeC8ducSqJIT95DWSbZ7mzF74ELdB2912dbJCIEcSc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8CxyOhHi25lFe4+AA--.24171S3; Tue, 05 Dec 2023 10:30:31 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9xBi25lVglVAA--.56558S4; Tue, 05 Dec 2023 10:30:31 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v2 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code. Date: Tue, 5 Dec 2023 10:30:19 +0800 Message-Id: <20231205023019.32452-3-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231205023019.32452-1-chenglulu@loongson.cn> References: <20231205023019.32452-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9xBi25lVglVAA--.56558S4 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWfGr1xZF1kGFWUCF4fWr4rJFc_yoWDtw15pF 9ruwsxtr48GrsxWr4Dt3s5WwnrJ3srKr17X3WftF18Ca17Xr18ZF48GFZxXF1jqa9Yqry2 qryFkw43Za1jkacCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8gAw7UUUUU== X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org The instructions defined in LoongArch Reference Manual v1.1 are not the instruction set v1.1 version. The CPU defined later may only support some instructions in LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and related definitions are removed here. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro. (fill_native_cpu_config): Define a new variable hw_isa_evolution record the extended instruction set support read from cpucfg. * config/loongarch/loongarch-def.cc: Set evolution at initialization. * config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete. (ISA_BASE_LA64V110): Likewise. (N_ISA_BASE_TYPES): Likewise. (defined): Likewise. * config/loongarch/loongarch-opts.cc: Likewise. * config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise. (ISA_BASE_IS_LA64V110): Likewise. * config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise. * config/loongarch/loongarch.opt: Regenerate. --- .../loongarch/genopts/loongarch-strings | 1 - gcc/config/loongarch/genopts/loongarch.opt.in | 3 --- gcc/config/loongarch/loongarch-cpu.cc | 23 +++++-------------- gcc/config/loongarch/loongarch-def.cc | 14 +++++++---- gcc/config/loongarch/loongarch-def.h | 12 ++-------- gcc/config/loongarch/loongarch-opts.cc | 3 --- gcc/config/loongarch/loongarch-opts.h | 4 +--- gcc/config/loongarch/loongarch-str.h | 1 - gcc/config/loongarch/loongarch.opt | 3 --- 9 files changed, 19 insertions(+), 45 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index b2070c83ed0..7bc4824007e 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -30,7 +30,6 @@ STR_CPU_LA664 la664 # Base architecture STR_ISA_BASE_LA64V100 la64 -STR_ISA_BASE_LA64V110 la64v1.1 # -mfpu OPTSTR_ISA_EXT_FPU fpu diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 8af6cc6f532..483b185b059 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -32,9 +32,6 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) -EnumValue -Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110) - ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index 622df47916f..4033320d0e1 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -23,7 +23,6 @@ along with GCC; see the file COPYING3. If not see #include "config.h" #include "system.h" #include "coretypes.h" -#include "tm.h" #include "diagnostic-core.h" #include "loongarch-def.h" @@ -32,19 +31,6 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-cpucfg-map.h" #include "loongarch-str.h" -/* loongarch_isa_base_features defined here instead of loongarch-def.c - because we need to use options.h. Pay attention on the order of elements - in the initializer becaue ISO C++ does not allow C99 designated - initializers! */ - -#define ISA_BASE_LA64V110_FEATURES \ - (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \ - | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS) - -int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { - /* [ISA_BASE_LA64V100] = */ 0, - /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES, -}; /* Native CPU detection with "cpucfg" */ static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 }; @@ -235,18 +221,20 @@ fill_native_cpu_config (struct loongarch_target *tgt) /* Use the native value anyways. */ preset.simd = tmp; + + int64_t hw_isa_evolution = 0; + /* Features added during ISA evolution. */ for (const auto &entry: cpucfg_map) if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit) - preset.evolution |= entry.isa_evolution_bit; + hw_isa_evolution |= entry.isa_evolution_bit; if (native_cpu_type != CPU_NATIVE) { /* Check if the local CPU really supports the features of the base ISA of probed native_cpu_type. If any feature is not detected, either GCC or the hardware is buggy. */ - auto base_isa_feature = loongarch_isa_base_features[preset.base]; - if ((preset.evolution & base_isa_feature) != base_isa_feature) + if ((preset.evolution & hw_isa_evolution) != hw_isa_evolution) warning (0, "detected base architecture %qs, but some of its " "features are not detected; the detected base " @@ -254,6 +242,7 @@ fill_native_cpu_config (struct loongarch_target *tgt) "features will be enabled", loongarch_isa_base_strings[preset.base]); } + preset.evolution = hw_isa_evolution; } if (tune_native_p) diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc index 6990c86c2c4..bc6997e45b5 100644 --- a/gcc/config/loongarch/loongarch-def.cc +++ b/gcc/config/loongarch/loongarch-def.cc @@ -18,6 +18,11 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" + #include "loongarch-def.h" #include "loongarch-str.h" @@ -51,9 +56,11 @@ array_arch loongarch_cpu_default_isa = .simd_ (ISA_EXT_SIMD_LASX)) .set (CPU_LA664, loongarch_isa () - .base_ (ISA_BASE_LA64V110) + .base_ (ISA_BASE_LA64V100) .fpu_ (ISA_EXT_FPU64) - .simd_ (ISA_EXT_SIMD_LASX)); + .simd_ (ISA_EXT_SIMD_LASX) + .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA + | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)); static inline loongarch_cache la464_cache () { @@ -136,8 +143,7 @@ array_tune loongarch_cpu_multipass_dfa_lookahead = array_tune () array loongarch_isa_base_strings = array () - .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100) - .set (ISA_BASE_LA64V110, STR_ISA_BASE_LA64V110); + .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100); array loongarch_isa_ext_strings = array () diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 68a9a461e54..a2c86df5bd9 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -56,19 +56,11 @@ along with GCC; see the file COPYING3. If not see /* enum isa_base */ /* LoongArch V1.00. */ -#define ISA_BASE_LA64V100 0 -/* LoongArch V1.10. */ -#define ISA_BASE_LA64V110 1 -#define N_ISA_BASE_TYPES 2 +#define ISA_BASE_LA64V100 0 +#define N_ISA_BASE_TYPES 1 extern loongarch_def_array loongarch_isa_base_strings; -#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) -/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is - we cannot use the C++ header options.h in loongarch-def.c. */ -extern int64_t loongarch_isa_base_features[]; -#endif - /* enum isa_ext_* */ #define ISA_EXT_NONE 0 #define ISA_EXT_FPU32 1 diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 7b63ef57a2a..8689f2dab05 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -285,9 +285,6 @@ config_target_isa: /* Get default ISA from "-march" or its default value. */ t.isa = loongarch_cpu_default_isa[t.cpu_arch]; - if (t.cpu_arch != CPU_NATIVE) - t.isa.evolution |= loongarch_isa_base_features[t.isa.base]; - /* Apply incremental changes. */ /* "-march=native" overrides the default FPU type. */ diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index e1ec702335d..651c1c18ca8 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -77,8 +77,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) #define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) -#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \ - || la_target.isa.base == ISA_BASE_LA64V110) +#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) @@ -90,7 +89,6 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) #define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664) -#define ISA_BASE_IS_LA64V110 (la_target.isa.base == ISA_BASE_LA64V110) /* Note: optimize_size may vary across functions, while -m[no]-memcpy imposes a global constraint. */ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 0384493765c..7c78d1443d5 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -33,7 +33,6 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_LA664 "la664" #define STR_ISA_BASE_LA64V100 "la64" -#define STR_ISA_BASE_LA64V110 "la64v1.1" #define OPTSTR_ISA_EXT_FPU "fpu" #define STR_NONE "none" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 4d36e3ec4de..41e6424e861 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -40,9 +40,6 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100) -EnumValue -Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110) - ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int)