From patchwork Mon Dec 4 13:32:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 81283 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1C449385AC21 for ; Mon, 4 Dec 2023 13:32:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id BDFA7385841A for ; Mon, 4 Dec 2023 13:32:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BDFA7385841A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 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01400000000000G0V000000A0000000 X-QQ-FEAT: LE7C6P2vL8QqL/SEQM58kxKGBu3X7uJzpbNUVngMkKfhhxXUJBpkHdgjkN2CQ /WiwXoqoagsYoTICCyRw3kqM8Bp/0Ok4vKdCVQ6YD5D7rX7tVjyWSdod+rGbTe4hbsuJxoq CFuV2Ccbv0nk1VE1koUej86w+ajmoIatHJzyinMqxyPT0X0Bz/7kqNYcjXZ2kyzsIR7+W2P 6qXr902rQ6giKf2dTjxrbUuFO5c+vP/0ZrDWOBZfdyQaU9Jimnmd7VBeh4AMOvk81jFB8ec kT4tlaHC6Lv2nqWAbksWXbeVz4kiLGtT/lhYuKdLEycL2cmr/n61chpYjjfv43zIYGrfF5b QwlObBGR+GwwY9M5MXv8NejgVV6C4u/VYnpRYulohr5ooldmX1IfXC5e46ZvWTqExV0ZF9L XxqmqCUjd/s= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 9200830303338088993 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Support highest-number regno overlap for widen ternary Date: Mon, 4 Dec 2023 21:32:06 +0800 Message-Id: <20231204133206.444790-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Consider this example: #include "riscv_vector.h" void foo6 (void *in, void *out) { vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4); vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1); vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64); vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i); vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i); vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32, 4); __riscv_vse64_v_f64m8 (out, result, 4); } Before this patch: foo6: # @foo6 vsetivli zero, 4, e32, m4, ta, ma vle64.v v8, (a0) lui a0, 272384 fmv.w.x fa5, a0 vmv8r.v v16, v8 vfwnmsac.vf v16, fa5, v12 vse64.v v16, (a1) ret After this patch: foo6: .LFB5: .cfi_startproc lui a5,%hi(.LC0) flw fa5,%lo(.LC0)(a5) vsetivli zero,4,e32,m4,ta,ma vle64.v v8,0(a0) vfwnmsac.vf v8,fa5,v12 vse64.v v8,0(a1) ret PR target/112431 gcc/ChangeLog: * config/riscv/vector.md: Add highest-number overlap support. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-37.c: New test. * gcc.target/riscv/rvv/base/pr112431-38.c: New test. --- gcc/config/riscv/vector.md | 115 +++++++++--------- .../gcc.target/riscv/rvv/base/pr112431-37.c | 103 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-38.c | 82 +++++++++++++ 3 files changed, 245 insertions(+), 55 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 72cf3553e45..ee222980bed 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5866,29 +5866,30 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (any_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ"))) (any_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0")) (match_dup 2)))] "TARGET_VECTOR" - "vwmacc.vx\t%0,%3,%4%p1" + "vwmacc.vx\t%0,%z3,%4%p1" [(set_attr "type" "viwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) (define_insn "@pred_widen_mul_plussu" [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") @@ -5915,54 +5916,56 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mul_plussu_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (sign_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ"))) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0")) (match_dup 2)))] "TARGET_VECTOR" - "vwmaccsu.vx\t%0,%3,%4%p1" + "vwmaccsu.vx\t%0,%z3,%4%p1" [(set_attr "type" "viwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) (define_insn "@pred_widen_mul_plusus_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ"))) (sign_extend:VWEXTI - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0")) (match_dup 2)))] "TARGET_VECTOR" - "vwmaccus.vx\t%0,%3,%4%p1" + "vwmaccus.vx\t%0,%z3,%4%p1" [(set_attr "type" "viwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated BOOL mask operations @@ -7181,15 +7184,15 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_widen_mul__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) @@ -7197,17 +7200,18 @@ (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: - (match_operand: 3 "register_operand" " f"))) + (match_operand: 3 "register_operand" " f, f, f, f, f, f, f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))) - (match_operand:VWEXTF 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0")) (match_dup 2)))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) + (symbol_ref "riscv_vector::get_frm_mode (operands[9])")) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) (define_insn "@pred_widen_mul_neg_" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") @@ -7239,15 +7243,15 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_widen_mul_neg__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) @@ -7256,17 +7260,18 @@ (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: - (match_operand: 3 "register_operand" " f"))) + (match_operand: 3 "register_operand" " f, f, f, f, f, f, f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) - (match_operand:VWEXTF 2 "register_operand" " 0")) + (match_operand: 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))) + (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0")) (match_dup 2)))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) + (symbol_ref "riscv_vector::get_frm_mode (operands[9])")) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point comparison operations diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c new file mode 100644 index 00000000000..6337ff875fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c @@ -0,0 +1,103 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out) +{ + vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4); + vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1); + vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16); + vint16m2_t result = __riscv_vwmacc_vx_i16m2 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m2 (out, result, 4); +} + +void +foo2 (void *in, void *out) +{ + vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4); + vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1); + vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16); + vint16m4_t result = __riscv_vwmacc_vx_i16m4 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m4 (out, result, 4); +} + +void +foo3 (void *in, void *out) +{ + vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4); + vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1); + vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16); + vint16m8_t result = __riscv_vwmacc_vx_i16m8 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m8 (out, result, 4); +} + +void +foo4 (void *in, void *out) +{ + vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4); + vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1); + vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16); + vint16m2_t result = __riscv_vwmaccus_vx_i16m2 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m2 (out, result, 4); +} + +void +foo5 (void *in, void *out) +{ + vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4); + vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1); + vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16); + vint16m4_t result = __riscv_vwmaccus_vx_i16m4 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m4 (out, result, 4); +} + +void +foo6 (void *in, void *out) +{ + vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4); + vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1); + vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16); + vint16m8_t result = __riscv_vwmaccus_vx_i16m8 (accum, 16, high_eew8, 4); + __riscv_vse16_v_i16m8 (out, result, 4); +} + +void +foo7 (void *in, void *out) +{ + vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4); + vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1); + vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16); + vuint8m1_t high_ueew8 = __riscv_vreinterpret_v_i8m1_u8m1 (high_eew8); + vint16m2_t result = __riscv_vwmaccsu_vx_i16m2 (accum, 16, high_ueew8, 4); + __riscv_vse16_v_i16m2 (out, result, 4); +} + +void +foo8 (void *in, void *out) +{ + vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4); + vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1); + vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16); + vuint8m2_t high_ueew8 = __riscv_vreinterpret_v_i8m2_u8m2 (high_eew8); + vint16m4_t result = __riscv_vwmaccsu_vx_i16m4 (accum, 16, high_ueew8, 4); + __riscv_vse16_v_i16m4 (out, result, 4); +} + +void +foo9 (void *in, void *out) +{ + vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4); + vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1); + vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16); + vuint8m4_t high_ueew8 = __riscv_vreinterpret_v_i8m4_u8m4 (high_eew8); + vint16m8_t result = __riscv_vwmaccsu_vx_i16m8 (accum, 16, high_ueew8, 4); + __riscv_vse16_v_i16m8 (out, result, 4); +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c new file mode 100644 index 00000000000..7b7d6cc7e98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c @@ -0,0 +1,82 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out) +{ + vfloat64m2_t accum = __riscv_vle64_v_f64m2 (in, 4); + vfloat64m1_t high_eew64 = __riscv_vget_v_f64m2_f64m1 (accum, 1); + vint64m1_t high_eew64_i = __riscv_vreinterpret_v_f64m1_i64m1 (high_eew64); + vint32m1_t high_eew32_i = __riscv_vreinterpret_v_i64m1_i32m1 (high_eew64_i); + vfloat32m1_t high_eew32 = __riscv_vreinterpret_v_i32m1_f32m1 (high_eew32_i); + vfloat64m2_t result = __riscv_vfwmacc_vf_f64m2 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m2 (out, result, 4); +} + +void +foo2 (void *in, void *out) +{ + vfloat64m4_t accum = __riscv_vle64_v_f64m4 (in, 4); + vfloat64m2_t high_eew64 = __riscv_vget_v_f64m4_f64m2 (accum, 1); + vint64m2_t high_eew64_i = __riscv_vreinterpret_v_f64m2_i64m2 (high_eew64); + vint32m2_t high_eew32_i = __riscv_vreinterpret_v_i64m2_i32m2 (high_eew64_i); + vfloat32m2_t high_eew32 = __riscv_vreinterpret_v_i32m2_f32m2 (high_eew32_i); + vfloat64m4_t result = __riscv_vfwmacc_vf_f64m4 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m4 (out, result, 4); +} + +void +foo3 (void *in, void *out) +{ + vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4); + vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1); + vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64); + vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i); + vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i); + vfloat64m8_t result = __riscv_vfwmacc_vf_f64m8 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m8 (out, result, 4); +} + +void +foo4 (void *in, void *out) +{ + vfloat64m2_t accum = __riscv_vle64_v_f64m2 (in, 4); + vfloat64m1_t high_eew64 = __riscv_vget_v_f64m2_f64m1 (accum, 1); + vint64m1_t high_eew64_i = __riscv_vreinterpret_v_f64m1_i64m1 (high_eew64); + vint32m1_t high_eew32_i = __riscv_vreinterpret_v_i64m1_i32m1 (high_eew64_i); + vfloat32m1_t high_eew32 = __riscv_vreinterpret_v_i32m1_f32m1 (high_eew32_i); + vfloat64m2_t result = __riscv_vfwnmsac_vf_f64m2 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m2 (out, result, 4); +} + +void +foo5 (void *in, void *out) +{ + vfloat64m4_t accum = __riscv_vle64_v_f64m4 (in, 4); + vfloat64m2_t high_eew64 = __riscv_vget_v_f64m4_f64m2 (accum, 1); + vint64m2_t high_eew64_i = __riscv_vreinterpret_v_f64m2_i64m2 (high_eew64); + vint32m2_t high_eew32_i = __riscv_vreinterpret_v_i64m2_i32m2 (high_eew64_i); + vfloat32m2_t high_eew32 = __riscv_vreinterpret_v_i32m2_f32m2 (high_eew32_i); + vfloat64m4_t result = __riscv_vfwnmsac_vf_f64m4 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m4 (out, result, 4); +} + +void +foo6 (void *in, void *out) +{ + vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4); + vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1); + vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64); + vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i); + vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i); + vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32, 4); + __riscv_vse64_v_f64m8 (out, result, 4); +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */