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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id r9-20020a62e409000000b006cbae51f335sm1998719pfh.144.2023.12.03.22.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Dec 2023 22:40:21 -0800 (PST) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com Cc: Kito Cheng Subject: [committed] RISC-V: Add sifive-x280 to -mcpu Date: Mon, 4 Dec 2023 14:40:18 +0800 Message-Id: <20231204064018.80048-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org x280 is one of SiFive core, and it release for a while, also upstream LLVM already support that. [1] https://www.sifive.com/cores/intelligence-x280 gcc/ChangeLog: * config/riscv/riscv-cores.def: Add sifive-x280. * doc/invoke.texi (RISC-V Options): Add sifive-x280 gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-sifive-x280.c: New test. --- gcc/config/riscv/riscv-cores.def | 1 + gcc/doc/invoke.texi | 2 +- .../gcc.target/riscv/mcpu-sifive-x280.c | 20 +++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-x280.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 91deabb6079..34df59e8d61 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -73,6 +73,7 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series") RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2fab4c5d71f..6fe63b5f999 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29776,7 +29776,7 @@ by particular CPU name. Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, -@samp{sifive-u54}, and @samp{sifive-u74}. +@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}. @opindex mtune @item -mtune=@var{processor-string} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-x280.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-x280.c new file mode 100644 index 00000000000..be6e13f810b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-x280.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */ +/* SiFive x280 => rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_c) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvl512b) \ + && defined(__riscv_v)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}