From patchwork Mon Dec 4 02:57:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feng Wang X-Patchwork-Id: 81243 X-Patchwork-Delegate: kito.cheng@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC43F3858C39 for ; Mon, 4 Dec 2023 02:59:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmty3ljk5ljewns4xndka.icoremail.net (zg8tmty3ljk5ljewns4xndka.icoremail.net [167.99.105.149]) by sourceware.org (Postfix) with ESMTP id 6E6E2385C30A for ; Mon, 4 Dec 2023 02:58:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6E6E2385C30A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6E6E2385C30A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=167.99.105.149 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701658715; cv=none; b=G/y5YQH5tOTZyi3wJzW1o03zPnhHXeeQ4EmKjs/vmvSkqcLxOKYuNPzlfD4dXBVz1rc95KUfNMxQsCHfxYoQNpm57FmdEu3DadNWCIb905Nhw5VaenNVT0SN7dlkgnUFt5vQYdlPl5Te9qUTSt7bCaao93grSqYLL0eEzj7LSM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701658715; c=relaxed/simple; bh=45qNVgDXgCMh5Pxgvn4vwLu8NNmnyPE10AA+w5/bALc=; h=From:To:Subject:Date:Message-Id; b=cSirUWL0TVcYxMx7fbOc8ap9F5BTti0Mo49crJwHnURmn1XCaZNnxSNmcdzrZZNQ5XOWbi4f44PcPezrGz48iejeX79sBEVjXA+jhx2Tf6FoonyPaS9IBcxDbJVIUR9X9a+NeguX4v0xJw0TtoY5H8g99oz4FrDaift61YXCUJo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgC3Qv39P21lJhYAAA--.1700S10; Mon, 04 Dec 2023 10:57:25 +0800 (CST) From: Feng Wang To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, jeffreyalaw@gmail.com, zhusonghe@eswincomputing.com, panciyan@eswincomputing.com, Feng Wang Subject: [PATCH 7/7] RISC-V: Add intrinsic functions for crypto vector Zvksh extension Date: Mon, 4 Dec 2023 02:57:09 +0000 Message-Id: <20231204025709.3783-7-wangfeng@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231204025709.3783-1-wangfeng@eswincomputing.com> References: <20231204025709.3783-1-wangfeng@eswincomputing.com> X-CM-TRANSID: TAJkCgC3Qv39P21lJhYAAA--.1700S10 X-Coremail-Antispam: 1UD129KBjvAXoWfCr47KF18Wr1fArWUAr4fKrg_yoW5XF1rZo Z5trs5ua1rur17urZ8uw4rWw1UXa1xJrsxX3Z5KF1DC3WxAw45K3W7Ka1UCF17tr4jvFZ8 uFs3ZFWxJFy8Jr1rn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOO7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI1I0E14v26r1q6r43MI8I 3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxV WUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8I cVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2js IE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZF pf9x0JUArcfUUUUU= X-CM-SenderInfo: pzdqwwxhqjqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch add the intrinsic functions(according to https://github.com/ riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/ vector-crypto/intrinsic_funcs.md) for crypto vector Zvksh extension. And all the test cases are added for api-testing. Co-Authored by: Songhe Zhu gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zvksh in riscv_implied_info. * config/riscv/riscv-vector-builtins-bases.cc (class vaeskf2): Add new function_base for Zvksh. (class vaeskf2_vsm3c): Ditto. (class vsm3me): Ditto. (BASE): Add Zvksh BASE declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct zvbb_zvbc_def): Add function_builder for Zvksh. (struct crypto_vv_def): Ditto. * config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable condition. * config/riscv/riscv-vector-crypto-builtins-functions.def (vsm4r): Add intrinsc def. (vsm3me): Ditto. (vsm3c): Ditto. * config/riscv/riscv.md: Add Zvksh ins name. * config/riscv/vector-crypto.md (sm3c): Add Zvksh md patterns. (@pred_vaeskf2_scalar): Ditto. (@pred_vi_nomaskedoff_scalar): Ditto. (@pred_vsm3me): Ditto. * config/riscv/vector.md: Add the corresponding attribute for Zvksh. gcc/testsuite/ChangeLog: * gcc.target/riscv/zvk/zvk.exp: * gcc.target/riscv/zvk/zvksh/vsm3c.c: New test. * gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c: New test. * gcc.target/riscv/zvk/zvksh/vsm3me.c: New test. * gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 1 + .../riscv/riscv-vector-builtins-bases.cc | 26 ++++++++-- .../riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-shapes.cc | 10 ++-- .../riscv-vector-crypto-builtins-avail.h | 1 + ...riscv-vector-crypto-builtins-functions.def | 5 +- gcc/config/riscv/riscv.md | 4 +- gcc/config/riscv/vector-crypto.md | 43 +++++++++++++--- gcc/config/riscv/vector.md | 12 ++--- gcc/testsuite/gcc.target/riscv/zvk/zvk.exp | 2 + .../gcc.target/riscv/zvk/zvksh/vsm3c.c | 51 +++++++++++++++++++ .../riscv/zvk/zvksh/vsm3c_overloaded.c | 51 +++++++++++++++++++ .../gcc.target/riscv/zvk/zvksh/vsm3me.c | 51 +++++++++++++++++++ .../riscv/zvk/zvksh/vsm3me_overloaded.c | 51 +++++++++++++++++++ 14 files changed, 286 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 87595b135ef..dbb42ca2f1e 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -128,6 +128,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvknha", "v"}, {"zvknhb", "v"}, {"zvksed", "v"}, + {"zvksh", "v"}, {"zfh", "zfhmin"}, {"zfhmin", "f"}, diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 83309f07661..07a9dc49104 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2302,8 +2302,9 @@ public: } }; -/* Implements vaeskf2. */ -class vaeskf2 : public function_base +/* Implements vaeskf2/vsm3c. */ +template +class vaeskf2_vsm3c : public function_base { public: bool apply_mask_policy_p () const override { return false; } @@ -2312,7 +2313,20 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn (code_for_pred_vaeskf2_scalar (e.vector_mode ())); + return e.use_exact_insn (code_for_pred_vi_nomaskedoff_scalar (UNSPEC, e.vector_mode ())); + } +}; + +/* Implements vsm3me. */ +class vsm3me : public function_base +{ +public: + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vsm3me (e.vector_mode ())); } }; @@ -2593,12 +2607,14 @@ static CONSTEXPR const crypto_vv vaesdf_obj; static CONSTEXPR const crypto_vv vaesdm_obj; static CONSTEXPR const crypto_vv vaesz_obj; static CONSTEXPR const crypto_vi vaeskf1_obj; -static CONSTEXPR const vaeskf2 vaeskf2_obj; +static CONSTEXPR const vaeskf2_vsm3c vaeskf2_obj; static CONSTEXPR const vg_nhab vsha2ms_obj; static CONSTEXPR const vg_nhab vsha2ch_obj; static CONSTEXPR const vg_nhab vsha2cl_obj; static CONSTEXPR const crypto_vi vsm4k_obj; static CONSTEXPR const crypto_vv vsm4r_obj; +static CONSTEXPR const vsm3me vsm3me_obj; +static CONSTEXPR const vaeskf2_vsm3c vsm3c_obj; /* Declare the function base NAME, pointing it to an instance of class _obj. */ @@ -2887,4 +2903,6 @@ BASE (vsha2ch) BASE (vsha2cl) BASE (vsm4k) BASE (vsm4r) +BASE (vsm3me) +BASE (vsm3c) } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index e9e6d7bfe7f..51b53a3d4a9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -306,6 +306,8 @@ extern const function_base *const vsha2ch; extern const function_base *const vsha2cl; extern const function_base *const vsm4k; extern const function_base *const vsm4r; +extern const function_base *const vsm3me; +extern const function_base *const vsm3c; } } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 4fe298917f6..0272a0d51cf 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -1009,7 +1009,7 @@ struct zvbb_zvbc_def : public build_base } }; -/* vghsh/vgmul/vaes* class. */ +/* vghsh/vgmul/vsha2ms/vsha2ch/vsha2cl/vsm3me/vaes* class. */ struct crypto_vv_def : public build_base { char *get_name (function_builder &b, const function_instance &instance, @@ -1019,13 +1019,15 @@ struct crypto_vv_def : public build_base if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) return nullptr; b.append_base_name (instance.base_name); - /* There is no op_type name in vghsh/vgmul/vaesz/vsha2ms/vsha2ch/vsha2cl overloaded intrinsic */ + /* There is no op_type name in vghsh/vgmul/vaesz/vsha2ms/vsha2ch/vsha2cl/ + vsm3me overloaded intrinsic */ if (!((strcmp (instance.base_name, "vghsh") == 0 || strcmp (instance.base_name, "vgmul") == 0 || strcmp (instance.base_name, "vaesz") == 0 || strcmp (instance.base_name, "vsha2ms") == 0 || strcmp (instance.base_name, "vsha2ch") == 0 - || strcmp (instance.base_name, "vsha2cl") == 0) + || strcmp (instance.base_name, "vsha2cl") == 0 + || strcmp (instance.base_name, "vsm3me") == 0) && overloaded_p)) b.append_name (operand_suffixes[instance.op_info->op]); if (!overloaded_p) @@ -1050,7 +1052,7 @@ struct crypto_vv_def : public build_base } }; -/* vaeskf1/vaeskf2/vsm4k class. */ +/* vaeskf1/vaeskf2/vsm4k/vsm3c class. */ struct crypto_vi_def : public build_base { char *get_name (function_builder &b, const function_instance &instance, diff --git a/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h b/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h index f09315923f3..c360c1d794f 100755 --- a/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h +++ b/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h @@ -20,5 +20,6 @@ AVAIL (zvkned, TARGET_ZVKNED) AVAIL (zvknha_or_zvknhb, TARGET_ZVKNHA || TARGET_ZVKNHB) AVAIL (zvknhb, TARGET_ZVKNHB) AVAIL (zvksed, TARGET_ZVKSED) +AVAIL (zvksh, TARGET_ZVKSH) } #endif diff --git a/gcc/config/riscv/riscv-vector-crypto-builtins-functions.def b/gcc/config/riscv/riscv-vector-crypto-builtins-functions.def index 67f3bf5284b..53be469b2e6 100755 --- a/gcc/config/riscv/riscv-vector-crypto-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-crypto-builtins-functions.def @@ -72,4 +72,7 @@ DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x2_ops, zvksed) DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x4_ops, zvksed) DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x8_ops, zvksed) -DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x16_ops, zvksed) \ No newline at end of file +DEF_VECTOR_CRYPTO_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x16_ops, zvksed) +//Zvksh +DEF_VECTOR_CRYPTO_FUNCTION (vsm3me, crypto_vv, none_tu_preds, u_vvv_crypto_sew32_ops, zvksh) +DEF_VECTOR_CRYPTO_FUNCTION (vsm3c, crypto_vi, none_tu_preds, u_vvv_size_crypto_sew32_ops, zvksh) \ No newline at end of file diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c076b82008a..2df2cb66455 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -454,6 +454,8 @@ ;; vsha2cl crypto vector SHA-2 two rounds of compression instructions ;; vsm4k crypto vector SM4 KeyExpansion instructions ;; vsm4r crypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3c crypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -475,7 +477,7 @@ vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll, vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, - vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r" + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md index 7bd4cd9f8b9..c62553d3292 100755 --- a/gcc/config/riscv/vector-crypto.md +++ b/gcc/config/riscv/vector-crypto.md @@ -37,6 +37,8 @@ UNSPEC_VSM4R UNSPEC_VSM4RVV UNSPEC_VSM4RVS + UNSPEC_VSM3ME + UNSPEC_VSM3C ]) (define_int_attr ror_rol [(UNSPEC_VROL "rol") (UNSPEC_VROR "ror")]) @@ -59,6 +61,8 @@ (define_int_attr vi_ins_name [(UNSPEC_VAESKF1 "aeskf1") (UNSPEC_VSM4K "sm4k")]) +(define_int_attr vi_ins1_name [(UNSPEC_VAESKF2 "aeskf2") (UNSPEC_VSM3C "sm3c")]) + (define_int_attr ins_type [(UNSPEC_VGMUL "vv") (UNSPEC_VAESEFVV "vv") (UNSPEC_VAESEMVV "vv") (UNSPEC_VAESDFVV "vv") (UNSPEC_VAESDMVV "vv") (UNSPEC_VAESEFVS "vs") @@ -83,6 +87,8 @@ (define_int_iterator UNSPEC_CRYPTO_VI [UNSPEC_VAESKF1 UNSPEC_VSM4K]) +(define_int_iterator UNSPEC_CRYPTO_VI1 [UNSPEC_VAESKF2 UNSPEC_VSM3C]) + ;; zvbb instructions patterns. ;; vandn.vv vandn.vx vrol.vv vrol.vx ;; vror.vv vror.vx vror.vi @@ -462,11 +468,11 @@ [(set_attr "type" "v") (set_attr "mode" "")]) -;; vaeskf2.vi -(define_insn "@pred_vaeskf2_scalar" +;; vaeskf2.vi vsm3c.vi +(define_insn "@pred_vi_nomaskedoff_scalar" [(set (match_operand:VSI 0 "register_operand" "=vd") (if_then_else:VSI - (unspec: + (unspec: [(match_operand 4 "vector_length_operand" "rK") (match_operand 5 "const_int_operand" " i") (match_operand 6 "const_int_operand" " i") @@ -475,9 +481,30 @@ (unspec:VSI [(match_operand:VSI 1 "register_operand" "0") (match_operand:VSI 2 "register_operand" "vr") - (match_operand: 3 "const_int_operand" " i")] UNSPEC_VAESKF2) + (match_operand: 3 "const_int_operand" " i")] UNSPEC_CRYPTO_VI1) (match_dup 1)))] - "TARGET_ZVKNED" - "vaeskf2.vi\t%0,%2,%3" - [(set_attr "type" "vaeskf2") - (set_attr "mode" "")]) \ No newline at end of file + "TARGET_ZVKNED || TARGET_ZVKSH" + "v.vi\t%0,%2,%3" + [(set_attr "type" "v") + (set_attr "mode" "")]) + +;; zvksh instructions patterns. +;; vsm3me.vv + +(define_insn "@pred_vsm3me" + [(set (match_operand:VSI 0 "register_operand" "=vd, vd") + (if_then_else:VSI + (unspec: + [(match_operand 4 "vector_length_operand" "rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VSI + [(match_operand:VSI 2 "register_operand" "vr, vr") + (match_operand:VSI 3 "register_operand" "vr, vr")] UNSPEC_VSM3ME) + (match_operand:VSI 1 "vector_merge_operand" "vu, 0")))] + "TARGET_ZVKSH" + "vsm3me.vv\t%0,%2,%3" + [(set_attr "type" "vsm3me") + (set_attr "mode" "")]) \ No newline at end of file diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 7fae91b3860..2dda02d96f3 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -54,7 +54,7 @@ vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ - vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r") + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") (const_string "true")] (const_string "false"))) @@ -78,7 +78,7 @@ vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ - vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r") + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") (const_string "true")] (const_string "false"))) @@ -707,7 +707,7 @@ (const_int 2) (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ - vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r") + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") (const_int 1) (eq_attr "type" "vimuladd,vfmuladd") @@ -747,7 +747,7 @@ vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\ vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\ - vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k") + vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") (const_int 4) ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. @@ -780,7 +780,7 @@ vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\ vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\ vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\ - vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k") + vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") (symbol_ref "riscv_vector::get_ta(operands[5])") ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. @@ -869,7 +869,7 @@ (const_int 9) (eq_attr "type" "vmsfs,vmidx,vcompress,vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,\ - vsm4k") + vsm4k,vsm3me,vsm3c") (const_int 6) (eq_attr "type" "vmpop,vmffs,vssegte,vclz,vctz") diff --git a/gcc/testsuite/gcc.target/riscv/zvk/zvk.exp b/gcc/testsuite/gcc.target/riscv/zvk/zvk.exp index 7d87b0c1bee..5e2778a51a8 100644 --- a/gcc/testsuite/gcc.target/riscv/zvk/zvk.exp +++ b/gcc/testsuite/gcc.target/riscv/zvk/zvk.exp @@ -48,5 +48,7 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/zvknhb/*.\[cS\]]] \ "" $DEFAULT_CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/zvksed/*.\[cS\]]] \ "" $DEFAULT_CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/zvksh/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS # All done. dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c.c b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c.c new file mode 100644 index 00000000000..1cea2489708 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksh -mabi=lp64d -O2 -Wno-psabi" } */ +#include +#include + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; +vuint32mf2_t test_vsm3c_vi_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32mf2(vd, vs2, 0, vl); +} + +vuint32m1_t test_vsm3c_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m1(vd, vs2, 0, vl); +} + +vuint32m2_t test_vsm3c_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m2(vd, vs2, 0, vl); +} + +vuint32m4_t test_vsm3c_vi_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m4(vd, vs2, 0, vl); +} + +vuint32m8_t test_vsm3c_vi_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m8(vd, vs2, 0, vl); +} + +vuint32mf2_t test_vsm3c_vi_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32mf2_tu(vd, vs2, 0, vl); +} + +vuint32m1_t test_vsm3c_vi_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m1_tu(vd, vs2, 0, vl); +} + +vuint32m2_t test_vsm3c_vi_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m2_tu(vd, vs2, 0, vl); +} + +vuint32m4_t test_vsm3c_vi_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m4_tu(vd, vs2, 0, vl); +} + +vuint32m8_t test_vsm3c_vi_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_vsm3c_vi_u32m8_tu(vd, vs2, 0, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*ta,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*tu,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsm3c\.vi\s+v[0-9]+,\s*v[0-9]+,0} 10 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c new file mode 100644 index 00000000000..01b4c0fbb95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksh -mabi=lp64d -O2 -Wno-psabi" } */ +#include +#include + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; +vuint32mf2_t test_vsm3c_vi_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_vsm3c(vd, vs2, 0, vl); +} + +vuint32m1_t test_vsm3c_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_vsm3c(vd, vs2, 0, vl); +} + +vuint32m2_t test_vsm3c_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_vsm3c(vd, vs2, 0, vl); +} + +vuint32m4_t test_vsm3c_vi_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_vsm3c(vd, vs2, 0, vl); +} + +vuint32m8_t test_vsm3c_vi_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_vsm3c(vd, vs2, 0, vl); +} + +vuint32mf2_t test_vsm3c_vi_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_vsm3c_tu(vd, vs2, 0, vl); +} + +vuint32m1_t test_vsm3c_vi_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_vsm3c_tu(vd, vs2, 0, vl); +} + +vuint32m2_t test_vsm3c_vi_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_vsm3c_tu(vd, vs2, 0, vl); +} + +vuint32m4_t test_vsm3c_vi_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_vsm3c_tu(vd, vs2, 0, vl); +} + +vuint32m8_t test_vsm3c_vi_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_vsm3c_tu(vd, vs2, 0, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*ta,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*tu,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsm3c\.vi\s+v[0-9]+,\s*v[0-9]+,0} 10 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me.c b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me.c new file mode 100644 index 00000000000..78fdf741643 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksh -mabi=lp64d -O2 -Wno-psabi" } */ +#include +#include + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; +vuint32mf2_t test_vsm3me_vv_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32mf2(vs2, vs1, vl); +} + +vuint32m1_t test_vsm3me_vv_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m1(vs2, vs1, vl); +} + +vuint32m2_t test_vsm3me_vv_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m2(vs2, vs1, vl); +} + +vuint32m4_t test_vsm3me_vv_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m4(vs2, vs1, vl); +} + +vuint32m8_t test_vsm3me_vv_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m8(vs2, vs1, vl); +} + +vuint32mf2_t test_vsm3me_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32mf2_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m1_t test_vsm3me_vv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m1_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m2_t test_vsm3me_vv_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m2_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m4_t test_vsm3me_vv_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m4_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m8_t test_vsm3me_vv_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_vsm3me_vv_u32m8_tu(maskedoff, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*ta,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*tu,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsm3me\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 10 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c new file mode 100644 index 00000000000..00c9cfe56ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksh -mabi=lp64d -O2 -Wno-psabi" } */ +#include +#include + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; +vuint32mf2_t test_vsm3me_vv_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_vsm3me(vs2, vs1, vl); +} + +vuint32m1_t test_vsm3me_vv_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_vsm3me(vs2, vs1, vl); +} + +vuint32m2_t test_vsm3me_vv_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_vsm3me(vs2, vs1, vl); +} + +vuint32m4_t test_vsm3me_vv_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_vsm3me(vs2, vs1, vl); +} + +vuint32m8_t test_vsm3me_vv_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_vsm3me(vs2, vs1, vl); +} + +vuint32mf2_t test_vsm3me_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_vsm3me_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m1_t test_vsm3me_vv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_vsm3me_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m2_t test_vsm3me_vv_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_vsm3me_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m4_t test_vsm3me_vv_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_vsm3me_tu(maskedoff, vs2, vs1, vl); +} + +vuint32m8_t test_vsm3me_vv_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_vsm3me_tu(maskedoff, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*ta,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s*zero,\s*[a-x0-9]+,\s*[a-x0-9]+,m[a-x0-9]+,\s*tu,\s*ma} 5 } } */ +/* { dg-final { scan-assembler-times {vsm3me\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 10 } } */ \ No newline at end of file