From patchwork Fri Dec 1 12:31:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 81109 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A22DB3858404 for ; Fri, 1 Dec 2023 12:32:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 529D2385AC36 for ; Fri, 1 Dec 2023 12:31:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 529D2385AC36 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 529D2385AC36 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701433923; cv=none; b=SEDExDak/odJ5sL5TtVec6m9p4JewrbkgnY9ZIFM2znccROPv/KBL9kWLVIxgHewm9glxhGHAdcT1x9sFxf0l3qou8BtxDTkPJa/4L/3jGbfnXqw8Hcle2wsaDcVfsTgbbviD0CtnknmUlhGivhJEuzQFpUzjP2pgEvgDx0KUBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701433923; c=relaxed/simple; bh=bGBvLSV2lJp37NGCEQP/IjbeDf1W2KDdeID9dkRzrrg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=f9K5AsWz5u/DtsSKKgPoao+pXhfOLgeVcxXWQyotjOGbe70ya79QADGYZgT5sAoqI/BEbziN61tXWbRRBrXOF6qgOUGsZ83ZprJkurcc1kBjcL3VfyQmQnrHkqj+TLjtr83JnNkFQwa9mz4mHp38338BKjvCxFSAh39C1rLuTWA= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp73t1701433913t631bops Received: from server1.localdomain ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Dec 2023 20:31:51 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: Pthanf+YHLZtWLT4Sf3wz5/MAjDfrM/wR6sP1Jh86l/RsO5nLR06k0uAFkUjs UnjHgP8wQnY0Qvn7ezoggU6AlLBrfut7N6qt5DNF3+KhzuEZQFpYiXsYBQgHYNecSn1Mkl6 qgKgM7suRPlrP6aRerUKrkYdhdslcMmI0khxUTndeniB/Z+RfsG4OM3/jq04ERqHcCa3kED Ou/LUxzRmfVtpsWvCFIv3yJ+uUa7oUnS7aInSnVJL0r07n5dAykDCwrpOefTH1X6wjJO/lf FkGlkB7sLShHfTmNMl5ZOUyZvKYIqmJ6Inq1kcWKp+7yq+0FwIA3RvkZKWJLegAb+H++y8o 35OCqLOBdwohf0RRrJbKkiIJkTne2uzf+zbR2wYJKSINJBSdEktR30Kvc4JwKZBt+5Tzy99 lOJhePLDVKUDErkuag7/yA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 18229726433194076243 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect combine of extended scalar pattern Date: Fri, 1 Dec 2023 20:31:50 +0800 Message-Id: <20231201123150.1940367-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Background: RVV ISA vx instructions for example vadd.vx, When EEW = 64 and RV32. We can't directly use vadd.vx. Instead, we need to use: sw sw vlse vadd.vv However, we have some special situation that we still can directly use vadd.vx directly for EEW=64 && RV32. that is, when scalar is a known CONST_INT value that doesn't overflow 32-bit value. So, we have a dedicated pattern for such situation: ... (sign_extend: (match_operand: 3 "register_operand" " r, r, r, r")). ... We first force_reg such CONST_INT (within 32bit value) into a SImode reg. Then use such special patterns. Those pattern with this operand match should only value on! TARGET_64BIT. The PR112801 combine into such patterns on RV64 incorrectly (Those patterns should be only value on RV32). This is the bug: andi a2,a2,2 vsetivli zero,2,e64,m1,ta,ma sext.w a3,a4 vmv.v.x v1,a2 vslide1down.vx v1,v1,a4 -> it should be a3 instead of a4. Such incorrect codegen is caused by ... (sign_extend:DI (subreg:SI (reg:DI 135 [ f.0_3 ]) 0)) ] UNSPEC_VSLIDE1DOWN)) 16935 {*pred_slide1downv2di_extended} ... Incorretly combine into the patterns should not be valid on RV64 system. So add !TARGET_64BIT to all same type patterns which can fix such issue as well as robostify the vector.md. PR target/112801 gcc/ChangeLog: * config/riscv/vector.md: Add !TARGET_64BIT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112801.c: New test. --- gcc/config/riscv/vector.md | 52 +++++++++---------- .../gcc.target/riscv/rvv/autovec/pr112801.c | 36 +++++++++++++ 2 files changed, 62 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112801.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 09e8a63af07..acb812593a0 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1913,7 +1913,7 @@ (match_operand:V_VLSI_D 2 "register_operand" " vr,vr") (match_operand: 4 "register_operand" " vm,vm")) (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmerge.vxm\t%0,%2,%3,%4" [(set_attr "type" "vimerge") (set_attr "mode" "")]) @@ -2091,7 +2091,7 @@ (sign_extend: (match_operand: 3 "register_operand" " r, r, r, r"))) (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "@ vmv.v.x\t%0,%3 vmv.v.x\t%0,%3 @@ -2677,7 +2677,7 @@ (match_operand: 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))) (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")) (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -2753,7 +2753,7 @@ (sign_extend: (match_operand: 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))) (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -2829,7 +2829,7 @@ (match_operand: 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))) (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")) (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vrsub.vx\t%0,%3,%z4%p1" [(set_attr "type" "vialu") (set_attr "mode" "")]) @@ -2947,7 +2947,7 @@ (match_operand: 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))) (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH) (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmulh.vx\t%0,%3,%z4%p1" [(set_attr "type" "vimul") (set_attr "mode" "")]) @@ -3126,7 +3126,7 @@ (match_operand:VI_D 2 "register_operand" "vr,vr")) (match_operand: 4 "register_operand" "vm,vm")] UNSPEC_VADC) (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vadc.vxm\t%0,%2,%z3,%4" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -3210,7 +3210,7 @@ (match_operand: 3 "reg_or_0_operand" "rJ,rJ")))) (match_operand: 4 "register_operand" "vm,vm")] UNSPEC_VSBC) (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vsbc.vxm\t%0,%2,%z3,%4" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -3360,7 +3360,7 @@ (match_operand 5 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmadc.vxm\t%0,%1,%z2,%3" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -3430,7 +3430,7 @@ (match_operand 5 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmsbc.vxm\t%0,%1,%z2,%3" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -3571,7 +3571,7 @@ (match_operand 4 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmadc.vx\t%0,%1,%z2" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -3638,7 +3638,7 @@ (match_operand 4 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vmsbc.vx\t%0,%1,%z2" [(set_attr "type" "vicalu") (set_attr "mode" "") @@ -4162,7 +4162,7 @@ (match_operand: 4 "register_operand" " r, r, r, r"))) (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "v.vx\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -4238,7 +4238,7 @@ (sign_extend: (match_operand: 4 "register_operand" " r, r, r, r")))) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "v.vx\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -4386,7 +4386,7 @@ (sign_extend: (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -4994,7 +4994,7 @@ (sign_extend: (match_operand: 4 "register_operand" " r")))]) (match_dup 1)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vms%B2.vx\t%0,%3,%4,v0.t" [(set_attr "type" "vicmp") (set_attr "mode" "") @@ -5020,7 +5020,7 @@ (sign_extend: (match_operand: 5 "register_operand" " r, r")))]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -5041,7 +5041,7 @@ (sign_extend: (match_operand: 5 "register_operand" " r, r, r, r, r")))]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -5062,7 +5062,7 @@ (match_operand: 4 "register_operand" " r"))) (match_operand:V_VLSI_D 3 "register_operand" " vr")]) (match_dup 1)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vms%B2.vx\t%0,%3,%4,v0.t" [(set_attr "type" "vicmp") (set_attr "mode" "") @@ -5088,7 +5088,7 @@ (match_operand: 5 "register_operand" " r, r"))) (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -5109,7 +5109,7 @@ (match_operand: 5 "register_operand" " r, r, r, r, r"))) (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -5489,7 +5489,7 @@ (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")) (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "@ vmadd.vx\t%0,%2,%4%p1 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1 @@ -5522,7 +5522,7 @@ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")) (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "@ vmacc.vx\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 @@ -5787,7 +5787,7 @@ (match_operand: 2 "register_operand" " r, r, r, r"))) (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))) (match_dup 3)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsub.vx\t%0,%2,%4%p1 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 @@ -5820,7 +5820,7 @@ (match_operand: 2 "register_operand" " r, r, r, r"))) (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsac.vx\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 @@ -8153,7 +8153,7 @@ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr") (sign_extend: (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_64BIT" "vslide.vx\t%0,%3,%z4%p1" [(set_attr "type" "vislide") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112801.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112801.c new file mode 100644 index 00000000000..eaf5c1c39d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112801.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-require-effective-target riscv_v } */ + +#include +int a; +void c(int b) { a = b; } +char d; +char *const e = &d; +long f = 66483309998; +unsigned long g[2]; +short h; +int k; +void __attribute__ ((noinline)) l() { + int i = 0; + for (; i < 2; i++) { + { + unsigned long *m = &g[0]; + *m &= 2; + if (f && *e) + for (;;) + ; + } + k = f; + g[1] = k; + for (; h;) + ; + } +} +int main() { + l(); + assert (g[1] == 2058800558); + c(g[1] >> 32); + assert (a == 0); +}