diff mbox series

i386: Fix CPUID of USER_MSR.

Message ID 20231129012125.458224-1-lin1.hu@intel.com
State Committed
Commit 88029286c35d3bf65568fea1324d595a15441772
Headers
Series i386: Fix CPUID of USER_MSR. |

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Commit Message

Hu, Lin1 Nov. 29, 2023, 1:21 a.m. UTC 
  Hi, all

This patch aims to fix the wrong CPUID of USER_MSR, its correct CPUID is
(0x7, 0x1).EDX[15], But I set it as (0x7, 0x0).EDX[15]. And the patch modefied
testcase for give the user a better example.

It has been bootstrapped and regtested on x86-64-pc-linux-gnu, OK for trunk?

BR,
Lin

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
	to the correct location.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user
	an proper example.
---
 gcc/common/config/i386/cpuinfo.h           | 4 ++--
 gcc/testsuite/gcc.target/i386/user_msr-1.c | 9 +++++----
 2 files changed, 7 insertions(+), 6 deletions(-)

Comments

Hongtao Liu Nov. 29, 2023, 2:43 a.m. UTC | #1 
On Wed, Nov 29, 2023 at 9:23 AM Hu, Lin1 <lin1.hu@intel.com> wrote:
>
> Hi, all
>
> This patch aims to fix the wrong CPUID of USER_MSR, its correct CPUID is
> (0x7, 0x1).EDX[15], But I set it as (0x7, 0x0).EDX[15]. And the patch modefied
> testcase for give the user a better example.
>
> It has been bootstrapped and regtested on x86-64-pc-linux-gnu, OK for trunk?
Ok.
>
> BR,
> Lin
>
> gcc/ChangeLog:
>
>         * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
>         to the correct location.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user
>         an proper example.
> ---
>  gcc/common/config/i386/cpuinfo.h           | 4 ++--
>  gcc/testsuite/gcc.target/i386/user_msr-1.c | 9 +++++----
>  2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
> index f90fb4d56a2..a1eb285daed 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -861,8 +861,6 @@ get_available_features (struct __processor_model *cpu_model,
>         set_feature (FEATURE_IBT);
>        if (edx & bit_UINTR)
>         set_feature (FEATURE_UINTR);
> -      if (edx & bit_USER_MSR)
> -       set_feature (FEATURE_USER_MSR);
>        if (amx_usable)
>         {
>           if (edx & bit_AMX_TILE)
> @@ -921,6 +919,8 @@ get_available_features (struct __processor_model *cpu_model,
>             set_feature (FEATURE_PREFETCHI);
>           if (eax & bit_RAOINT)
>             set_feature (FEATURE_RAOINT);
> +         if (edx & bit_USER_MSR)
> +           set_feature (FEATURE_USER_MSR);
>           if (avx_usable)
>             {
>               if (eax & bit_AVXVNNI)
> diff --git a/gcc/testsuite/gcc.target/i386/user_msr-1.c b/gcc/testsuite/gcc.target/i386/user_msr-1.c
> index 447852306df..f315016d088 100644
> --- a/gcc/testsuite/gcc.target/i386/user_msr-1.c
> +++ b/gcc/testsuite/gcc.target/i386/user_msr-1.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { ! ia32  }  }  } */
>  /* { dg-options "-musermsr -O2"  } */
>  /* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1  }  } */
> -/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$121" 1  }  } */
> +/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$6912" 1  }  } */
>  /* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1  }  } */
> -/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$121" 1  }  } */
> +/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$6912" 1  }  } */
>
>  #include <x86gprintrin.h>
>
> @@ -13,8 +13,9 @@ volatile unsigned long long y;
>  void extern
>  user_msr_test (void)
>  {
> +  y = 6913;
>    x = _urdmsr(y);
> -  x = _urdmsr(121);
> +  x = _urdmsr(6912);
>    _uwrmsr(y, x);
> -  _uwrmsr(121, x);
> +  _uwrmsr(6912, x);
>  }
> --
> 2.31.1
>
diff mbox series

Patch

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index f90fb4d56a2..a1eb285daed 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -861,8 +861,6 @@  get_available_features (struct __processor_model *cpu_model,
 	set_feature (FEATURE_IBT);
       if (edx & bit_UINTR)
 	set_feature (FEATURE_UINTR);
-      if (edx & bit_USER_MSR)
-	set_feature (FEATURE_USER_MSR);
       if (amx_usable)
 	{
 	  if (edx & bit_AMX_TILE)
@@ -921,6 +919,8 @@  get_available_features (struct __processor_model *cpu_model,
 	    set_feature (FEATURE_PREFETCHI);
 	  if (eax & bit_RAOINT)
 	    set_feature (FEATURE_RAOINT);
+	  if (edx & bit_USER_MSR)
+	    set_feature (FEATURE_USER_MSR);
 	  if (avx_usable)
 	    {
 	      if (eax & bit_AVXVNNI)
diff --git a/gcc/testsuite/gcc.target/i386/user_msr-1.c b/gcc/testsuite/gcc.target/i386/user_msr-1.c
index 447852306df..f315016d088 100644
--- a/gcc/testsuite/gcc.target/i386/user_msr-1.c
+++ b/gcc/testsuite/gcc.target/i386/user_msr-1.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { ! ia32  }  }  } */
 /* { dg-options "-musermsr -O2"  } */
 /* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1  }  } */
-/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$121" 1  }  } */
+/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$6912" 1  }  } */
 /* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1  }  } */
-/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$121" 1  }  } */
+/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$6912" 1  }  } */
 
 #include <x86gprintrin.h>
 
@@ -13,8 +13,9 @@  volatile unsigned long long y;
 void extern
 user_msr_test (void)
 {
+  y = 6913;
   x = _urdmsr(y);
-  x = _urdmsr(121);
+  x = _urdmsr(6912);
   _uwrmsr(y, x);
-  _uwrmsr(121, x);
+  _uwrmsr(6912, x);
 }