From patchwork Sat Nov 18 04:34:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 80203 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9290E3858C30 for ; Sat, 18 Nov 2023 04:34:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) by sourceware.org (Postfix) with ESMTPS id BB0623858D1E for ; Sat, 18 Nov 2023 04:34:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB0623858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BB0623858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.133 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700282074; cv=none; b=npPhrR55Gd7piCb8+IDIgDkRWXCrJ4/nLPmxrdGmWn5JjwNO9PgDSazXql+0LLwX8yuuxFPA/oxaNVflYK1TzCDYYh8Jv/M8ydgX5KCH4Kdpa6y+ZZp399puYQiJpk91jb5sJPmhjyqkAak5iFr7aeY7SyLaZ8oTIW6Tv3RPL4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700282074; c=relaxed/simple; bh=dBNWJ4dWJwJC8k0X756uiLFJMxjUcUwjzXWvaeRG7fc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=FshRf8A3CF9zX6Y3S7hKIxJuWbvHezmbfVWm1JXdaihYbR5lluuC73cai0xwd9PnuNCqSk3ssPsWX3KIXn9H80VxwwbD/G+l/qBkrbny1Kiay7G9TNfEUYQUMZr2DBGYNgeFK7ZhCcMBntaecGbliAW3tlZRHyQeSx9ZsJEvGFQ= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R271e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VwbPhaL_1700282060; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VwbPhaL_1700282060) by smtp.aliyun-inc.com; Sat, 18 Nov 2023 12:34:24 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" Subject: [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Date: Sat, 18 Nov 2023 12:34:11 +0800 Message-Id: <20231118043411.3810-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> References: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-21.1 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c: New test. --- .../rvv/xtheadvector/binop_vx_constraint-31.c | 73 +++++++++++ .../rvv/xtheadvector/binop_vx_constraint-32.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-33.c | 73 +++++++++++ .../rvv/xtheadvector/binop_vx_constraint-34.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-35.c | 73 +++++++++++ .../rvv/xtheadvector/binop_vx_constraint-36.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-37.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-38.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-39.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-40.c | 73 +++++++++++ .../rvv/xtheadvector/binop_vx_constraint-41.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-42.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-43.c | 68 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-44.c | 73 +++++++++++ .../rvv/xtheadvector/binop_vx_constraint-45.c | 123 ++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-46.c | 72 ++++++++++ .../rvv/xtheadvector/binop_vx_constraint-47.c | 16 +++ .../rvv/xtheadvector/binop_vx_constraint-48.c | 16 +++ .../rvv/xtheadvector/binop_vx_constraint-49.c | 16 +++ .../rvv/xtheadvector/binop_vx_constraint-50.c | 18 +++ 20 files changed, 1238 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c new file mode 100644 index 00000000000..66361ad567d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c new file mode 100644 index 00000000000..901e03bc181 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c new file mode 100644 index 00000000000..651244f7a0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c new file mode 100644 index 00000000000..25460cd3f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c new file mode 100644 index 00000000000..651244f7a0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c new file mode 100644 index 00000000000..25460cd3f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c new file mode 100644 index 00000000000..aca803f3930 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c new file mode 100644 index 00000000000..ce9261f67e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, -15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, -15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, -15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c new file mode 100644 index 00000000000..3adb7ae8f79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c new file mode 100644 index 00000000000..995b52130cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, 17, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, 17, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, 17, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c new file mode 100644 index 00000000000..7c4b1e78ca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c new file mode 100644 index 00000000000..b971a9af222 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c new file mode 100644 index 00000000000..ae23fa67f02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c new file mode 100644 index 00000000000..120230d1f2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c new file mode 100644 index 00000000000..cec8a0b8012 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcxtheadvector -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f0: +** ... +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c new file mode 100644 index 00000000000..7210890f20f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f0: +** ... +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c new file mode 100644 index 00000000000..0351e452d5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */ +#include "riscv_th_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c new file mode 100644 index 00000000000..3b849e906db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */ +#include "riscv_th_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c new file mode 100644 index 00000000000..4a18a410252 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */ +#include "riscv_th_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c new file mode 100644 index 00000000000..6713316fcab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */ +#include "riscv_th_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {th.vmv} } } */