From patchwork Fri Nov 17 20:43:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 80184 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 03A9A38432C8 for ; Fri, 17 Nov 2023 20:45:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id EE14F3858C2D for ; Fri, 17 Nov 2023 20:44:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE14F3858C2D Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EE14F3858C2D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253850; cv=none; b=BK8Y/XUfEsCRQUNH3DiiLOn1ldF9yK+WNWMIUOfT4hDolVozCB0r69+F7XE8s5HVYxB0lalg9NIkGB/wMPoSDQZNodwiGRPrCVUexRMwYYDDKfbeDvSj3tkuK8kgGH+WUvAA0EFBV3jym/f4uxU60DrP2Re1oDRJ2cESfLpzg+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253850; c=relaxed/simple; bh=BdUn1mWrgK26RjE4T6KIhG/PmXAvkL+iVs8fHuNx7GQ=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=E5nyuYlEHxxaVsEG0iHCRb3N5fl8tVDP/LiIBBnZzkVNrpbmanuK+c2g69kpx+7V5/2TDxyZI19HhnFF3OtAtPIZeQVuofgLQy9BaIM5PN/UV/X8MRF0FujXtgHrvuXJdyWEi2T+Qn9Pv4Qtu4PVzrNNc4LELlTMPbCsFKZfyf8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700253848; bh=BdUn1mWrgK26RjE4T6KIhG/PmXAvkL+iVs8fHuNx7GQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZbjEE74etsY4r9X5K6yBHC5O1Sb1BRSBWSGb+xH2iQffWBTW1C6VIKsCccALGOzIV +7ft7keGY9am5hq2DoAk/kHp8jT8B1e0DxSe5g+o681aI2+ct+WoP16HjQCtqGOR/W Iz3arjr/pWLY4TidhBGwdHa0Qo0cf802tew2Rn0c= Received: from stargazer.. (unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 96D7666B3B; Fri, 17 Nov 2023 15:44:05 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions Date: Sat, 18 Nov 2023 04:43:20 +0800 Message-ID: <20231117204323.453536-4-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org * config/loongarch/loongarch-def.h: (loongarch_isa_base_features): Declare. Define it in ... * config/loongarch/loongarch-cpu.cc (loongarch_isa_base_features): ... here. (fill_native_cpu_config): If we know the base ISA of the CPU model from PRID, use it instead of la64 (v1.0). Check if all expected features of this base ISA is available, emit a warning if not. * config/loongarch/loongarch-opts.cc (config_target_isa): Enable the features implied by the base ISA if not -march=native. --- gcc/config/loongarch/loongarch-cpu.cc | 62 ++++++++++++++++++-------- gcc/config/loongarch/loongarch-def.h | 5 +++ gcc/config/loongarch/loongarch-opts.cc | 3 ++ 3 files changed, 52 insertions(+), 18 deletions(-) diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index f41e175257a..7acf1a9121d 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -32,6 +32,19 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-cpucfg-map.h" #include "loongarch-str.h" +/* loongarch_isa_base_features defined here instead of loongarch-def.c + because we need to use options.h. Pay attention on the order of elements + in the initializer becaue ISO C++ does not allow C99 designated + initializers! */ + +#define ISA_BASE_LA64V110_FEATURES \ + (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA) + +int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { + /* [ISA_BASE_LA64V100] = */ 0, + /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES, +}; + /* Native CPU detection with "cpucfg" */ static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 }; @@ -127,24 +140,22 @@ fill_native_cpu_config (struct loongarch_target *tgt) With: base architecture (ARCH) At: cpucfg_words[1][1:0] */ - switch (cpucfg_cache[1] & 0x3) - { - case 0x02: - tmp = ISA_BASE_LA64V100; - break; - - default: - fatal_error (UNKNOWN_LOCATION, - "unknown native base architecture %<0x%x%>, " - "%qs failed", (unsigned int) (cpucfg_cache[1] & 0x3), - "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE); - } - - /* Check consistency with PRID presets. */ - if (native_cpu_type != CPU_NATIVE && tmp != preset.base) - warning (0, "base architecture %qs differs from PRID preset %qs", - loongarch_isa_base_strings[tmp], - loongarch_isa_base_strings[preset.base]); + if (native_cpu_type != CPU_NATIVE) + tmp = loongarch_cpu_default_isa[native_cpu_type].base; + else + switch (cpucfg_cache[1] & 0x3) + { + case 0x02: + tmp = ISA_BASE_LA64V100; + break; + + default: + fatal_error (UNKNOWN_LOCATION, + "unknown native base architecture %<0x%x%>, " + "%qs failed", + (unsigned int) (cpucfg_cache[1] & 0x3), + "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE); + } /* Use the native value anyways. */ preset.base = tmp; @@ -227,6 +238,21 @@ fill_native_cpu_config (struct loongarch_target *tgt) for (const auto &entry: cpucfg_map) if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit) preset.evolution |= entry.isa_evolution_bit; + + if (native_cpu_type != CPU_NATIVE) + { + /* Check if the local CPU really supports the features of the base + ISA of probed native_cpu_type. If any feature is not detected, + either GCC or the hardware is buggy. */ + auto base_isa_feature = loongarch_isa_base_features[preset.base]; + if ((preset.evolution & base_isa_feature) != base_isa_feature) + warning (0, + "detected base architecture %qs, but some of its " + "features are not detected; the detected base " + "architecture may be unreliable, only detected " + "features will be enabled", + loongarch_isa_base_strings[preset.base]); + } } if (tune_native_p) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 6123c8e0f19..af7bd635d6e 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -55,12 +55,17 @@ extern "C" { /* enum isa_base */ extern const char* loongarch_isa_base_strings[]; + /* LoongArch V1.00. */ #define ISA_BASE_LA64V100 0 /* LoongArch V1.10. */ #define ISA_BASE_LA64V110 1 #define N_ISA_BASE_TYPES 2 +/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is + we cannot use the C++ header options.h in loongarch-def.c. */ +extern int64_t loongarch_isa_base_features[]; + /* enum isa_ext_* */ extern const char* loongarch_isa_ext_strings[]; #define ISA_EXT_NONE 0 diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 67a59152a01..b5836f198c0 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -284,6 +284,9 @@ config_target_isa: /* Get default ISA from "-march" or its default value. */ t.isa = loongarch_cpu_default_isa[t.cpu_arch]; + if (t.cpu_arch != CPU_NATIVE) + t.isa.evolution |= loongarch_isa_base_features[t.isa.base]; + /* Apply incremental changes. */ /* "-march=native" overrides the default FPU type. */