From patchwork Fri Nov 17 09:01:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 80110 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DA56438449DD for ; Fri, 17 Nov 2023 09:02:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id E26C63858C41 for ; Fri, 17 Nov 2023 09:02:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E26C63858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E26C63858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700211734; cv=none; b=FsbHYEr2CnVj+hyWSC2qdbHsrKNHeMdXMVBEv4XvqBZYuGEu9ptRWeXOls+zvIfqMOUOSB3HTO/OK36xkz4nw8SmwOSTVYt5/pv5iL/+tF8S2a/4VTQtlA/AiZNqJVT42/5i4przvknJQMzQjLqf5uOhSMdtWGHkmPtNQuksX98= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700211734; c=relaxed/simple; bh=0C/6XpbnqxIJICxTnG5V/TnDZp3Lcub81oghacBwGsg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JWHeljtKvwEenmtmIR+EiQ9rwXE4khMMbaCuym+H08Hjl4T3N4m+YaVxP5RwEQuQRz+v6Muz7I2HJaXLI8OVUOU3P4cr8s0JOD08bJecMSkHKgMCboqNoeHAXqNnRIyRllsH/ahhjk5glasNtFbmr+AGvSFQw/dPrNHIdM255SE= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R941e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VwZO04d_1700211724; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VwZO04d_1700211724) by smtp.aliyun-inc.com; Fri, 17 Nov 2023 17:02:08 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" Subject: [PATCH 7/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part5) Date: Fri, 17 Nov 2023 17:01:53 +0800 Message-Id: <20231117090153.3135-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231117081955.2395-1-cooper.joshua@linux.alibaba.com> References: <20231117081955.2395-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.9 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for auto-vectorization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c: New test. * gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h: New test. --- .../rvv/xtheadvector/autovec/vadd-run-nofm.c | 4 + .../riscv/rvv/xtheadvector/autovec/vadd-run.c | 81 +++++++++++++++++++ .../xtheadvector/autovec/vadd-rv32gcv-nofm.c | 10 +++ .../rvv/xtheadvector/autovec/vadd-rv32gcv.c | 8 ++ .../xtheadvector/autovec/vadd-rv64gcv-nofm.c | 10 +++ .../rvv/xtheadvector/autovec/vadd-rv64gcv.c | 8 ++ .../rvv/xtheadvector/autovec/vadd-template.h | 70 ++++++++++++++++ .../rvv/xtheadvector/autovec/vadd-zvfh-run.c | 54 +++++++++++++ .../riscv/rvv/xtheadvector/autovec/vand-run.c | 75 +++++++++++++++++ .../rvv/xtheadvector/autovec/vand-rv32gcv.c | 7 ++ .../rvv/xtheadvector/autovec/vand-rv64gcv.c | 7 ++ .../rvv/xtheadvector/autovec/vand-template.h | 61 ++++++++++++++ 12 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c new file mode 100644 index 00000000000..b6328d0ad65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ + +#include "vadd-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c new file mode 100644 index 00000000000..ba453d18c66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c @@ -0,0 +1,81 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vadd-template.h" + +#include + +#define SZ 512 + +#define RUN(TYPE,VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = 0; \ + b##TYPE[i] = VAL; \ + } \ + vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == VAL); + +#define RUN2(TYPE,VAL) \ + TYPE as##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as##TYPE[i] = 0; \ + vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as##TYPE[i] == VAL); + +#define RUN3(TYPE,VAL) \ + TYPE ai##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + ai##TYPE[i] = VAL; \ + vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (ai##TYPE[i] == VAL + 15); + +#define RUN3M(TYPE,VAL) \ + TYPE aim##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + aim##TYPE[i] = VAL; \ + vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (aim##TYPE[i] == VAL - 16); + +#define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ + RUN(int16_t, -1) \ + RUN(uint16_t, 2) \ + RUN(int32_t, -3) \ + RUN(uint32_t, 4) \ + RUN(int64_t, -5) \ + RUN(uint64_t, 6) \ + RUN(float, -5) \ + RUN(double, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ + RUN2(int16_t, -7) \ + RUN2(uint16_t, 8) \ + RUN2(int32_t, -9) \ + RUN2(uint32_t, 10) \ + RUN2(int64_t, -11) \ + RUN2(uint64_t, 12) \ + RUN2(float, -11) \ + RUN2(double, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ + RUN3M(int16_t, 13) \ + RUN3(uint16_t, 14) \ + RUN3M(int32_t, 15) \ + RUN3(uint32_t, 16) \ + RUN3M(int64_t, 17) \ + RUN3(uint64_t, 18) \ + RUN3(float, 17) \ + RUN3M(double, 18) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c new file mode 100644 index 00000000000..eef83196be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gc_zvfh_xtheadvector -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ + +#include "vadd-template.h" + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c new file mode 100644 index 00000000000..7c9e857cc46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gc_zvfh_xtheadvector -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vadd-template.h" + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c new file mode 100644 index 00000000000..6a51d657013 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gc_zvfh_xtheadvector -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ + +#include "vadd-template.h" + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ + +/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c new file mode 100644 index 00000000000..62250731536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gc_zvfh_xtheadvector -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vadd-template.h" + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h new file mode 100644 index 00000000000..e05b9c76275 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h @@ -0,0 +1,70 @@ +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b[i]; \ + } + +#define TEST2_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b; \ + } + +#define TEST3_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vaddi_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + 15; \ + } + +#define TEST3M_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vaddim_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] - 16; \ + } + +#define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) \ + TEST_TYPE(_Float16) \ + TEST_TYPE(float) \ + TEST_TYPE(double) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ + TEST2_TYPE(int16_t) \ + TEST2_TYPE(uint16_t) \ + TEST2_TYPE(int32_t) \ + TEST2_TYPE(uint32_t) \ + TEST2_TYPE(int64_t) \ + TEST2_TYPE(uint64_t) \ + TEST2_TYPE(_Float16) \ + TEST2_TYPE(float) \ + TEST2_TYPE(double) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ + TEST3M_TYPE(int16_t) \ + TEST3_TYPE(uint16_t) \ + TEST3M_TYPE(int32_t) \ + TEST3_TYPE(uint32_t) \ + TEST3M_TYPE(int64_t) \ + TEST3_TYPE(uint64_t) \ + TEST3M_TYPE(_Float16) \ + TEST3_TYPE(float) \ + TEST3M_TYPE(double) \ + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c new file mode 100644 index 00000000000..2a8618ad09b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c @@ -0,0 +1,54 @@ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vadd-template.h" + +#include + +#define SZ 512 + +#define RUN(TYPE,VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = 0; \ + b##TYPE[i] = VAL; \ + } \ + vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == VAL); + +#define RUN2(TYPE,VAL) \ + TYPE as##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as##TYPE[i] = 0; \ + vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as##TYPE[i] == VAL); + +#define RUN3(TYPE,VAL) \ + TYPE ai##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + ai##TYPE[i] = VAL; \ + vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (ai##TYPE[i] == VAL + 15); + +#define RUN3M(TYPE,VAL) \ + TYPE aim##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + aim##TYPE[i] = VAL; \ + vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (aim##TYPE[i] == VAL - 16); + +#define RUN_ALL() \ + RUN(_Float16, 4) \ + RUN2(_Float16, 10) \ + RUN3M(_Float16, 17) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c new file mode 100644 index 00000000000..848b6eb77f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vand-template.h" + +#include + +#define SZ 512 + +#define RUN(TYPE,VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = 123; \ + b##TYPE[i] = VAL; \ + } \ + vand_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == (TYPE)(123 & VAL)); + +#define RUN2(TYPE,VAL) \ + TYPE as##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as##TYPE[i] = 123; \ + vands_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as##TYPE[i] == (123 & VAL)); + +#define RUN3(TYPE,VAL) \ + TYPE ai##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + ai##TYPE[i] = VAL; \ + vandi_##TYPE (ai##TYPE, ai##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (ai##TYPE[i] == (VAL & 15)); + +#define RUN3M(TYPE,VAL) \ + TYPE aim##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + aim##TYPE[i] = VAL; \ + vandim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (aim##TYPE[i] == (VAL & -16)); + +#define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ + RUN(int16_t, -1) \ + RUN(uint16_t, 2) \ + RUN(int32_t, -3) \ + RUN(uint32_t, 4) \ + RUN(int64_t, -5) \ + RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ + RUN2(int16_t, -7) \ + RUN2(uint16_t, 8) \ + RUN2(int32_t, -9) \ + RUN2(uint32_t, 10) \ + RUN2(int64_t, -11) \ + RUN2(uint64_t, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ + RUN3M(int16_t, 13) \ + RUN3(uint16_t, 14) \ + RUN3M(int32_t, 15) \ + RUN3(uint32_t, 16) \ + RUN3M(int64_t, 17) \ + RUN3(uint64_t, 18) + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c new file mode 100644 index 00000000000..058dc9d86df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcxtheadvector -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vand-template.h" + +/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c new file mode 100644 index 00000000000..def833e8b48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcxtheadvector -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "vand-template.h" + +/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h new file mode 100644 index 00000000000..e2409594f39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h @@ -0,0 +1,61 @@ +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +#define TEST2_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vands_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b; \ + } + +#define TEST3_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vandi_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & 15; \ + } + +#define TEST3M_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vandim_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & -16; \ + } + +#define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ + TEST2_TYPE(int16_t) \ + TEST2_TYPE(uint16_t) \ + TEST2_TYPE(int32_t) \ + TEST2_TYPE(uint32_t) \ + TEST2_TYPE(int64_t) \ + TEST2_TYPE(uint64_t) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ + TEST3M_TYPE(int16_t) \ + TEST3_TYPE(uint16_t) \ + TEST3M_TYPE(int32_t) \ + TEST3_TYPE(uint32_t) \ + TEST3M_TYPE(int64_t) \ + TEST3_TYPE(uint64_t) + +TEST_ALL()