From patchwork Fri Jun 9 07:53:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 70812 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F14973856DC7 for ; Fri, 9 Jun 2023 07:53:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F14973856DC7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686297216; bh=iSrWj+hFs13nBxDhfe5KxC5c2iOG3VScVuAC/9k0ujA=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=ut12Z5/PsU8yKsyagVE5dEO2Xwb6/OXMKhWvPz2a5pszCB68R9kPOt4BD7cZi6Ig6 5tBiK383P2mEBVnBInCI58n1Lp5qGnQiAtyydbqV7js0K1z7hzBGQiU1m01/fNCHdz HB2Hx6ybn14ykLWXdMrEwuVmJl1UWxLeYlMGEPho= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 4982D3858C20 for ; Fri, 9 Jun 2023 07:53:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4982D3858C20 X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="357546283" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="357546283" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2023 00:53:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="800134154" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="800134154" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by FMSMGA003.fm.intel.com with ESMTP; 09 Jun 2023 00:53:04 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 8B175100726C; Fri, 9 Jun 2023 15:53:03 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Fix one warning of frm enum. Date: Fri, 9 Jun 2023 15:53:01 +0800 Message-Id: <20230609075301.2214833-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Pan Li This patch would like to fix one warning similar as below, and add the link for where the values comes from. ./gcc/config/riscv/riscv-protos.h:260:13: warning: binary constants are a C++14 feature or GCC extension FRM_RNE = 0b000, ^~~~~ Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-protos.h (enum frm_field_enum): Adjust literal to int. Signed-off-by: Pan Li Signed-off-by: Pan Li > --- gcc/config/riscv/riscv-protos.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 38e4125424b..66c1f535d60 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -254,15 +254,18 @@ enum vxrm_field_enum VXRM_RDN, VXRM_ROD }; -/* Rounding mode bitfield for floating point FRM. */ +/* Rounding mode bitfield for floating point FRM. The value of enum comes + from the below link. + https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register + */ enum frm_field_enum { - FRM_RNE = 0b000, - FRM_RTZ = 0b001, - FRM_RDN = 0b010, - FRM_RUP = 0b011, - FRM_RMM = 0b100, - FRM_DYN = 0b111 + FRM_RNE = 0, /* Aka 0b000. */ + FRM_RTZ = 1, /* Aka 0b001. */ + FRM_RDN = 2, /* Aka 0b010. */ + FRM_RUP = 3, /* Aka 0b011. */ + FRM_RMM = 4, /* Aka 0b100. */ + FRM_DYN = 7, /* Aka 0b111. */ }; opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,