From patchwork Fri Jun 9 05:59:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 70805 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E9B98385696E for ; Fri, 9 Jun 2023 06:00:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E9B98385696E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686290436; bh=yzcgdn4FLFbtGag1t84eIOjYphTE4Lstbl1h0lsyQbc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=IfuBp7zh3yVaDWKdcrDCFUHoDLuBmx5joWTx8YJMYEf0J60Qi2dSbASv2tg3hKvOq uG28OlgW6+LDLKdGTsrFH+8ekPXAIWuiHsAPNJHTgNZ+RmitquwflkEIqKgiAjm68p q+93NYt6f0JIJcEc7qqCjNChllXQunv9FteV8h0g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 2F141385703C for ; Fri, 9 Jun 2023 06:00:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2F141385703C X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="443890415" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="443890415" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2023 23:00:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="854630589" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="854630589" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga001.fm.intel.com with ESMTP; 08 Jun 2023 23:00:02 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 3D0851007251; Fri, 9 Jun 2023 14:00:02 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Date: Fri, 9 Jun 2023 13:59:48 +0800 Message-Id: <20230609055948.1744603-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606123646.1553843-1-pan2.li@intel.com> References: <20230606123646.1553843-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Pan Li This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the iterators of RVV. And then the ZVFH will leverage one define attr the gate for FP16 supported or not. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li Co-Authored by: Juzhe-Zhong Co-Authored by: Kito Cheng gcc/ChangeLog: * config/riscv/riscv.md (ext): Move to another place. (ext_enabled): Ditto. (fp_vector_disabled): New define attr. (enabled): Add fp_vector_disabled to the cond. * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test for ZVFHMIN. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li > Signed-off-by: Pan Li > --- gcc/config/riscv/riscv.md | 84 ++++++++++++------- gcc/config/riscv/vector-iterators.md | 23 ++--- .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++- 3 files changed, 81 insertions(+), 41 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 38b8fba2a53..d1c7c3a3008 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes" (const_string "yes")] (const_string "no"))) -;; ISA attributes. -(define_attr "ext" "base,f,d,vector" - (const_string "base")) - -;; True if the extension is enabled. -(define_attr "ext_enabled" "no,yes" - (cond [(eq_attr "ext" "base") - (const_string "yes") - - (and (eq_attr "ext" "f") - (match_test "TARGET_HARD_FLOAT")) - (const_string "yes") - - (and (eq_attr "ext" "d") - (match_test "TARGET_DOUBLE_FLOAT")) - (const_string "yes") - - (and (eq_attr "ext" "vector") - (match_test "TARGET_VECTOR")) - (const_string "yes") - ] - (const_string "no"))) - -;; Attribute to control enable or disable instructions. -(define_attr "enabled" "no,yes" - (cond [(eq_attr "ext_enabled" "no") - (const_string "no")] - (const_string "yes"))) - ;; Classification of each insn. ;; branch conditional branch ;; jump unconditional jump @@ -434,6 +405,61 @@ (define_attr "type" (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] (const_string "unknown"))) +;; ISA attributes. +(define_attr "ext" "base,f,d,vector" + (const_string "base")) + +;; True if the extension is enabled. +(define_attr "ext_enabled" "no,yes" + (cond [(eq_attr "ext" "base") + (const_string "yes") + + (and (eq_attr "ext" "f") + (match_test "TARGET_HARD_FLOAT")) + (const_string "yes") + + (and (eq_attr "ext" "d") + (match_test "TARGET_DOUBLE_FLOAT")) + (const_string "yes") + + (and (eq_attr "ext" "vector") + (match_test "TARGET_VECTOR")) + (const_string "yes") + ] + (const_string "no"))) + +;; True if the float point vector is disabled. +(define_attr "fp_vector_disabled" "no,yes" + (cond [ + (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv, + vfwalu,vfwmul,vfmuladd,vfwmuladd, + vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp, + vfclass,vfmerge, + vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof, + vfredo,vfredu,vfwredo,vfwredu, + vfslide1up,vfslide1down") + (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF") + (match_test "!TARGET_ZVFH"))) + (const_string "yes") + + (and (eq_attr "type" "vfncvtftoi,vfwcvtitof") + (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI") + (match_test "!TARGET_ZVFH"))) + (const_string "yes") + ] + (const_string "no"))) + +;; Attribute to control enable or disable instructions. +(define_attr "enabled" "no,yes" + (cond [ + (eq_attr "ext_enabled" "no") + (const_string "no") + + (eq_attr "fp_vector_disabled" "yes") + (const_string "no") + ] + (const_string "yes"))) + ;; Length of instruction in bytes. (define_attr "length" "" (cond [ diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index f4946d84449..234b712bc9d 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") (VNx16HF "TARGET_VECTOR_ELEN_FP_16") (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ (define_mode_iterator V_FRACT [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") + + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c index 0923b6bc4d2..f1a29b639e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c @@ -3,6 +3,8 @@ #include "riscv_vector.h" +typedef _Float16 float16_t; + vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { return __riscv_vfncvt_f_f_w_f16mf4(src, vl); } @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { return __riscv_vfwcvt_f_f_v_f32m8(src, vl); } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) { + return __riscv_vle16_v_f16mf4(base, vl); +} + +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { + return __riscv_vle16_v_f16m8(base, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */ - +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */