From patchwork Sun Jun 4 09:36:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 70569 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BB6733858291 for ; Sun, 4 Jun 2023 09:37:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id D28153858D32 for ; Sun, 4 Jun 2023 09:36:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D28153858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1685871411t40aljdu Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 04 Jun 2023 17:36:49 +0800 (CST) X-QQ-SSF: 01400000000000F0S000000A0000000 X-QQ-FEAT: 3M0okmaRx3gqlM1HN44zWlNi0Zq21gVLHy1gGNWa7eByKt0HQVK2O0XOEUduI GxmnxbjgPwusAQWHixNlp7hdIywDkKcO2sd9hXItvwErMsnJQUKv75skekx7wnsVNCWA7AF MuyoPyRGsngd7MaMFjJj4YNfH2FiEy60CqlVsftYRuoiSJIfaTg1HhLQX7ozkLaAYqaVKji 0ewBFfeVD6NGdIif3wnRiRtkL6ALZkmk356zKnWJxX94mOKN5dwXlBv9xUqcWFcLS78n8Xm qhpnBWLxV4JgU+BnSk+4pI3ysYWaV4zfNR52SkFko5X5zfQ9M7VldOp+qQyL5jMYAer97dZ EcYTpNK1ImLjpXziqm33kWvNsVbGix1LfzgLqP/9sp0D+n7bFLgyDaO1OlVrMNRENIiF32f pmZ876Gm5QU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6044518482983892405 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [NFC] RISC-V: Move optimization patterns into autovec-opt.md Date: Sun, 4 Jun 2023 17:36:47 +0800 Message-Id: <20230604093647.4018890-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Move all optimization patterns into autovec-opt.md to make organization easier maintain. gcc/ChangeLog: * config/riscv/autovec-opt.md (*not): Move to autovec-opt.md. (*n): Ditto. * config/riscv/autovec.md (*not): Ditto. (*n): Ditto. * config/riscv/vector.md: Ditto. --- gcc/config/riscv/autovec-opt.md | 92 +++++++++++++++++++++++++++++++++ gcc/config/riscv/autovec.md | 52 ------------------- gcc/config/riscv/vector.md | 39 -------------- 3 files changed, 92 insertions(+), 91 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 92cdc4e9a16..f6052b50572 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -78,3 +78,95 @@ "vwmulsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmul") (set_attr "mode" "")]) + +;; ----------------------------------------------------------------------------- +;; ---- Integer Compare Instructions Simplification +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMCLR.m Includes: +;; - 1. VMSNE +;; - 2. VMSLT +;; - 3. VMSLTU +;; - 4. VMSGT +;; - 5. VMSGTU +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMSET.m Includes: +;; - 1. VMSEQ +;; - 2. VMSLE +;; - 3. VMSLEU +;; - 4. VMSGE +;; - 5. VMSGEU +;; ----------------------------------------------------------------------------- + +(define_split + [(set (match_operand:VB 0 "register_operand") + (if_then_else:VB + (unspec:VB + [(match_operand:VB 1 "vector_all_trues_mask_operand") + (match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VB 3 "vector_move_operand") + (match_operand:VB 2 "vector_undef_operand")))] + "TARGET_VECTOR" + [(const_int 0)] + { + emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), + RVV_VUNDEF (mode), operands[3], + operands[4], operands[5])); + DONE; + } +) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted second input) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmandnot.mm +;; - vmornot.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*not" + [(set (match_operand:VB 0 "register_operand" "=vr") + (bitmanip_bitwise:VB + (not:VB (match_operand:VB 2 "register_operand" " vr")) + (match_operand:VB 1 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted result) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmnand.mm +;; - vmnor.mm +;; - vmxnor.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*n" + [(set (match_operand:VB 0 "register_operand" "=vr") + (not:VB + (any_bitwise:VB + (match_operand:VB 1 "register_operand" " vr") + (match_operand:VB 2 "register_operand" " vr"))))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index ec038fe87cd..9f4492db23c 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -229,58 +229,6 @@ [(set_attr "type" "vmalu") (set_attr "mode" "")]) -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted second input) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmandnot.mm -;; - vmornot.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*not" - [(set (match_operand:VB 0 "register_operand" "=vr") - (bitmanip_bitwise:VB - (not:VB (match_operand:VB 2 "register_operand" " vr")) - (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_not (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted result) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmnand.mm -;; - vmnor.mm -;; - vmxnor.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*n" - [(set (match_operand:VB 0 "register_operand" "=vr") - (not:VB - (any_bitwise:VB - (match_operand:VB 1 "register_operand" " vr") - (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_n (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - ;; ========================================================================= ;; == Comparisons and selects ;; ========================================================================= diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 2496eff7874..0f6aeac8852 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8297,44 +8297,5 @@ [(set_attr "type" "vssegtx") (set_attr "mode" "")]) -;; ----------------------------------------------------------------------------- -;; ---- Integer Compare Instructions Simplification -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMCLR.m Includes: -;; - 1. VMSNE -;; - 2. VMSLT -;; - 3. VMSLTU -;; - 4. VMSGT -;; - 5. VMSGTU -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMSET.m Includes: -;; - 1. VMSEQ -;; - 2. VMSLE -;; - 3. VMSLEU -;; - 4. VMSGE -;; - 5. VMSGEU -;; ----------------------------------------------------------------------------- -(define_split - [(set (match_operand:VB 0 "register_operand") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand") - (match_operand 4 "vector_length_operand") - (match_operand 5 "const_int_operand") - (match_operand 6 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VB 3 "vector_move_operand") - (match_operand:VB 2 "vector_undef_operand")))] - "TARGET_VECTOR" - [(const_int 0)] - { - emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), - RVV_VUNDEF (mode), operands[3], - operands[4], operands[5])); - DONE; - } -) - (include "autovec.md") (include "autovec-opt.md")