From patchwork Fri Jun 2 06:31:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 70495 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 23D163857701 for ; Fri, 2 Jun 2023 06:32:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 94D353858C53 for ; Fri, 2 Jun 2023 06:31:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 94D353858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1685687504tjjscxgc Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 02 Jun 2023 14:31:43 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: 5QxEZ1enDv/BsSNAQtRlUZ5dxCBvFVvq5rHosXCbvn6ZEUtgZQYvUzxm5dG0k E3TorliHuFdhfztq3vofSx4OaBNUGsng8wyr0+L6HR1ohHrb04TrPcileBTOX7NDBFQaTgq IRQ4FJHdsT8bCtySwdAVnGs2GJ4f6WCStq4TmujtfQ3Erj4glbczzyawXYnH1pJg96HkO2f rkvszQi+1ubOSd+J44t7qDd8LNF1cJK5owMF3MUgMbzEsxt9d8UOQiFn+DYhn8+w/H09rHg DI4DovczYpcmZvL0I5lQbHtFkzR2/ZKNhm71eUeP2Uw2nF/3UK/sHm9Ia0lHSCdwbl13vYZ 4H3i2a881SQWze5Cp0vgezW9Si3MptDaQu341rquR3G8yghq+NIrOlJhZmBzn8mhlqp8uV7 U1QflN3x+Mtz/VPR196+6w== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13221081490105774826 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Optimize reverse series index vector Date: Fri, 2 Jun 2023 14:31:40 +0800 Message-Id: <20230602063140.29401-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong This patch optimizes the following seriese vector: [nunits - 1, nunits - 2, ...., 0] Before this patch: vid vmul vadd After this patch: vid vrsub This patch is an obvious and simple optimization, ok for trunk? gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_series): Optimize reverse series index vector. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Add assembly check. --- gcc/config/riscv/riscv-v.cc | 17 +++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/perm-4.c | 2 ++ 2 files changed, 19 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 1cd3bd3438e..75cf00b7eba 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -530,6 +530,8 @@ expand_vec_series (rtx dest, rtx base, rtx step) machine_mode mode = GET_MODE (dest); machine_mode mask_mode; gcc_assert (get_mask_mode (mode).exists (&mask_mode)); + poly_int64 nunits_m1 = GET_MODE_NUNITS (mode) - 1; + poly_int64 value; /* VECT_IV = BASE + I * STEP. */ @@ -545,6 +547,21 @@ expand_vec_series (rtx dest, rtx base, rtx step) rtx step_adj; if (rtx_equal_p (step, const1_rtx)) step_adj = vid; + else if (rtx_equal_p (step, constm1_rtx) && poly_int_rtx_p (base, &value) + && known_eq (nunits_m1, value)) + { + /* Special case: + {nunits - 1, nunits - 2, ... , 0}. + nunits can be either const_int or const_poly_int. + + Code sequence: + vid.v v + vrsub nunits - 1, v. */ + rtx ops[] = {dest, vid, gen_int_mode (nunits_m1, GET_MODE_INNER (mode))}; + insn_code icode = code_for_pred_sub_reverse_scalar (mode); + emit_vlmax_insn (icode, RVV_BINOP, ops); + return; + } else { step_adj = gen_reg_rtx (mode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c index 179c8274a92..aa328810c30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c @@ -56,3 +56,5 @@ TEST_ALL (PERMUTE) /* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */ +/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */ +/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */