From patchwork Thu Jun 1 23:19:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 70483 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 765C23858C2C for ; Thu, 1 Jun 2023 23:19:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id DDEFA3858C50 for ; Thu, 1 Jun 2023 23:19:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DDEFA3858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1685661550tuwc4g3h Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 02 Jun 2023 07:19:09 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: QityeSR92A365chCBlYmCCuJni6pO5PIvITBJkGP0/Gp55uDzAdVU6lKIn9JE CLAoQO0Y2Hcp3V5lpJl5VUHzhAJ+66Y9qtV2KZDivbA7Dgeqxvn9YD1UpA71yeZnu1+qNKu UFS62Iqlw7xhohX+gq/Rb7iUplq2qEyx1G7XNzMVcGM2aSczSJSIn9Yz5gAlMxjyEKgp4+N ubarQr91cFHug04j7ArTc7PDQIbtG8+FEMn0HX0+m6i6qgUQ0rQmXKLd+2ZvPdGB0UHa3BW 4I4qOFBzNxQ+zyib+23xhtt+77qF1vo8yZMeaS+UzdrDFkD473eEE+Ht5zikHRZPPOBuk7Y Aa2WZhmls+is7vzcRWanaURkx3ZkWKADtSb97Ruz9Hqchu3XgdOCrsR+w/QNjNUaOTPHIxw X-QQ-GoodBg: 2 X-BIZMAIL-ID: 89594278007164039 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add __RISCV_ prefix to VXRM and FRM enum Date: Fri, 2 Jun 2023 07:19:07 +0800 Message-Id: <20230601231907.3879-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong According to doc: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226 Add __RISCV_ prefix to VXRM and FRM enum. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add __RISCV_ prefix. (DEF_RVV_FRM_ENUM): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/frm-1.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-1.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-10.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-11.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-12.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-6.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-7.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-8.c: Ditto. * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto. --- gcc/config/riscv/riscv-vector-builtins.cc | 8 ++++---- gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c | 8 ++++---- 10 files changed, 31 insertions(+), 31 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 43bf6d8f262..9e6dae98a6d 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4026,11 +4026,11 @@ register_vxrm () { auto_vec values; #define DEF_RVV_VXRM_ENUM(NAME, VALUE) \ - values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE)); + values.quick_push (string_int_pair ("__RISCV_VXRM_" #NAME, VALUE)); #include "riscv-vector-builtins.def" #undef DEF_RVV_VXRM_ENUM - lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values); + lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_VXRM", &values); } /* Register the frm enum. */ @@ -4039,11 +4039,11 @@ register_frm () { auto_vec values; #define DEF_RVV_FRM_ENUM(NAME, VALUE) \ - values.quick_push (string_int_pair ("FRM_" #NAME, VALUE)); + values.quick_push (string_int_pair ("__RISCV_FRM_" #NAME, VALUE)); #include "riscv-vector-builtins.def" #undef DEF_RVV_FRM_ENUM - lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values); + lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_FRM", &values); } /* Implement #pragma riscv intrinsic vector. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c index f5635fb959e..ff19c8bc089 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c @@ -5,27 +5,27 @@ size_t f0 () { - return FRM_RNE; + return __RISCV_FRM_RNE; } size_t f1 () { - return FRM_RTZ; + return __RISCV_FRM_RTZ; } size_t f2 () { - return FRM_RDN; + return __RISCV_FRM_RDN; } size_t f3 () { - return FRM_RUP; + return __RISCV_FRM_RUP; } size_t f4 () { - return FRM_RMM; + return __RISCV_FRM_RMM; } /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c index 0d364787ad0..b0ed27b0520 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c @@ -5,22 +5,22 @@ size_t f0 () { - return VXRM_RNU; + return __RISCV_VXRM_RNU; } size_t f1 () { - return VXRM_RNE; + return __RISCV_VXRM_RNE; } size_t f2 () { - return VXRM_RDN; + return __RISCV_VXRM_RDN; } size_t f3 () { - return VXRM_ROD; + return __RISCV_VXRM_ROD; } /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c index a707aa1645e..3c7872bb73d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c @@ -8,16 +8,16 @@ void f (void * in, void *out, int32_t x, int n, int m) for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RNE, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RNE, 4); __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c index 7f637a8b7f5..2cbd548eeb6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c @@ -10,9 +10,9 @@ void f (void * in, void *out, int32_t x, int n, int m) for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); fn (); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c index c3ab509f106..95a58ca6b90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c @@ -8,9 +8,9 @@ void f (void * in, void *out, int32_t x, int n, int m) for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); asm volatile ("csrwi\tvxrm,1"); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c index 4b346d67c27..6ef469fdce8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c @@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n, int m) { vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100, v3, 4); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c index 1ca795ce3f4..50902c37a55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c @@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n, int m) { vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100, v3, 4); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c index 5799f731e21..3ed0d00d1e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c @@ -8,8 +8,8 @@ void f (void * in, void *out, int32_t x, int n, int m) for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c index 13921d4af21..0939705b2e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c @@ -8,16 +8,16 @@ void f (void * in, void *out, int32_t x, int n, int m) for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4); - vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); - v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4); } }