From patchwork Wed May 31 15:08:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 70393 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9548A3857006 for ; Wed, 31 May 2023 15:09:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTPS id 00F423857709 for ; Wed, 31 May 2023 15:09:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 00F423857709 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [43.139.163.53]) by APP-01 (Coremail) with SMTP id qwCowAA3PZkGY3dkmJ3uCA--.9691S2; Wed, 31 May 2023 23:08:55 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: palmer@dabbelt.com, kito.cheng@sifive.com, jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, dje.gcc@gmail.com, mirimmad@outlook.com, pinskia@gmail.com, jeffreyalaw@gmail.com, lidie@eswincomputing.com, yulong Subject: [PATCH V2] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c Date: Wed, 31 May 2023 23:08:43 +0800 Message-Id: <20230531150843.20585-1-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: qwCowAA3PZkGY3dkmJ3uCA--.9691S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr47XFWDXr4xuFW5AFW7twb_yoWxurWDpa 1ftw1fZryftryjkwnxKryFyF1rAF40qryFya1qq3W7KrZ7AryUXr10kw18t3ZIgry7urWa ya1UKFn7Ar4jvw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9v14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwAKzVCY07xG64k0F24lc2xSY4AK6cvj6ryrMxAIw28IcxkI7VAKI48JMxC20s 026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_ JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14 v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xva j40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JV W8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUb3CztUUUUU== X-Originating-IP: [43.139.163.53] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to solve it. In this patch, I take Kito's advice that I modify the form of the function bodies.It likes *[a-x0-9]. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv32.c:Modify * gcc.target/riscv/xtheadcondmov-indirect-rv64.c:Modify --- .../riscv/xtheadcondmov-indirect-rv32.c | 50 +++++++++---------- .../riscv/xtheadcondmov-indirect-rv64.c | 50 +++++++++---------- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c index e2b135f3d00..d0df59c5e1c 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c @@ -5,9 +5,9 @@ /* **ConEmv_imm_imm_reg: -** addi a5,a0,-1000 -** li a0,10 -** th.mvnez a0,a1,a5 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** li\t\s*[a-x0-9]+,10+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_imm_imm_reg(int x, int y){ @@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){ /* **ConEmv_imm_reg_reg: -** addi a5,a0,-1000 -** th.mveqz a2,a1,a5 -** mv a0,a2 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_imm_reg_reg(int x, int y, int z){ @@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){ /* **ConEmv_reg_imm_reg: -** sub a1,a0,a1 -** li a0,10 -** th.mvnez a0,a2,a1 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** li\t\s*[a-x0-9]+,10+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_reg_imm_reg(int x, int y, int z){ @@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){ /* **ConEmv_reg_reg_reg: -** sub a1,a0,a1 -** th.mveqz a3,a2,a1 -** mv a0,a3 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ @@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ /* **ConNmv_imm_imm_reg: -** addi a5,a0,-1000 -** li a0,9998336 -** addi a0,a0,1664 -** th.mveqz a0,a1,a5 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** li\t\s*[a-x0-9]+,9998336+ +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_imm_imm_reg(int x, int y){ @@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){ /* **ConNmv_imm_reg_reg: -** addi a0,a0,-1000 -** th.mvnez a2,a1,a0 -** mv a0,a2 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_imm_reg_reg(int x, int y, int z){ @@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){ /* **ConNmv_reg_imm_reg: -** sub a1,a0,a1 -** li a0,10 -** th.mveqz a0,a2,a1 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** li\t\s*[a-x0-9]+,10+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_reg_imm_reg(int x, int y, int z){ @@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){ /* **ConNmv_reg_reg_reg: -** sub a0,a0,a1 -** th.mvnez a3,a2,a0 -** mv a0,a3 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_reg_reg_reg(int x, int y, int z, int n){ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c index 99956f8496c..cc971a75ace 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c @@ -5,9 +5,9 @@ /* **ConEmv_imm_imm_reg: -** addi a5,a0,-1000 -** li a0,10 -** th.mvnez a0,a1,a5 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** li\t\s*[a-x0-9]+,10+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_imm_imm_reg(int x, int y){ @@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){ /* **ConEmv_imm_reg_reg: -** addi a0,a0,-1000 -** th.mveqz a2,a1,a5 -** mv a0,a2 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_imm_reg_reg(int x, int y, int z){ @@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){ /* **ConEmv_reg_imm_reg: -** sub a1,a0,a1 -** li a0,10 -** th.mvnez a0,a2,a1 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** li\t\s*[a-x0-9]+,10+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_reg_imm_reg(int x, int y, int z){ @@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){ /* **ConEmv_reg_reg_reg: -** sub a1,a0,a1 -** th.mveqz a3,a2,a1 -** mv a0,a3 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ @@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){ /* **ConNmv_imm_imm_reg: -** addi a5,a0,-1000 -** li a0,9998336 -** addi a0,a0,1664 -** th.mveqz a0,a1,a5 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** li\t\s*[a-x0-9]+,9998336+ +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_imm_imm_reg(int x, int y){ @@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){ /* **ConNmv_imm_reg_reg: -** addi a5,a0,-1000 -** th.mvnez a2,a1,a0 -** mv a0,a2 +** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_imm_reg_reg(int x, int y, int z){ @@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){ /* **ConNmv_reg_imm_reg: -** sub a1,a0,a1 -** li a0,10 -** th.mveqz a0,a2,a1 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** li\t\s*[a-x0-9]+,10+ +** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_reg_imm_reg(int x, int y, int z){ @@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){ /* **ConNmv_reg_reg_reg: -** sub a0,a0,a1 -** th.mvnez a3,a2,a0 -** mv a0,a3 +** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+ +** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+ ** ret */ int ConNmv_reg_reg_reg(int x, int y, int z, int n){