From patchwork Fri May 12 09:38:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 69229 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A4D253893C4A for ; Fri, 12 May 2023 09:43:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4D253893C4A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683884589; bh=NCXROoku7c7yR2pFa+ZSISgTl5KwidSoL/8z1c4E0wE=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=uiB+7PqA4hXroG3jfRqpaZF64bg6Ze63CcCdH4ry4B75gEMflabRN3XScMr47BR7U n9n6ynuPx7OXilnvTWVNAu5hn4mas6Q6p3jmw6FcuVsKnqqbuZpps5WFsHUi0q2AkZ V6JP/wwRPGAFfHb1wy0G6A4Cpq3s9yGZlOksA0AA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on2072.outbound.protection.outlook.com [40.107.14.72]) by sourceware.org (Postfix) with ESMTPS id 288EB38560B6 for ; Fri, 12 May 2023 09:39:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 288EB38560B6 Received: from DUZPR01CA0291.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b7::9) by DU2PR08MB10108.eurprd08.prod.outlook.com (2603:10a6:10:496::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.33; Fri, 12 May 2023 09:39:19 +0000 Received: from DBAEUR03FT025.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:4b7:cafe::67) by DUZPR01CA0291.outlook.office365.com (2603:10a6:10:4b7::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT025.mail.protection.outlook.com (100.127.142.226) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.18 via Frontend Transport; Fri, 12 May 2023 09:39:19 +0000 Received: ("Tessian outbound 945aec65ec65:v136"); Fri, 12 May 2023 09:39:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 67928cb637efa7d6 X-CR-MTA-TID: 64aa7808 Received: from 4723a4f96274.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 877DDA5F-435C-4CF8-9856-AF6CE832CDFE.1; Fri, 12 May 2023 09:39:13 +0000 Received: from EUR01-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 4723a4f96274.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 12 May 2023 09:39:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UJyYTrxyRXrdxXQKnJOGkflgjlrM/avPbsZpyXMDh2V6RhomWkJ0ZgPHzmzP9T9YcqLYt3sb3LPjwI67ucojxw3oSYZZPWaXiDTwJDvGIl06mLeVCReroXkgductzB8U9pzaDgiw1vqb6pD8O6SqAyIVq+33b819waqdRj9CyiFvh5gKjK7fplt/lOdH8mo67DVJDqP7B0iZV7yhUtk4ONy85dHICgHTToQkPwpL8NRdes08X3rC8rGtHI83ETZh+2fCpXEc11CUP7OrjudeVP08lUGHNTZwZYT9BJkwNvK5srCnkMm0PxXv/FMAn98IOkbyH50CMjbUE5DZHa+jnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NCXROoku7c7yR2pFa+ZSISgTl5KwidSoL/8z1c4E0wE=; b=gFEEweES+fvNJOEIe96iHKvDOPWvT44WdzHsOE6Dlz1CkqDGvQ9YZscf3gPE2vR+KZErfs9WAuvWQWjZVVfWmak6UlJwCix2QGjvZ/68A2NMsW6DQ3oEeT2m63Zq3mRtTPQYZm8kFE9mbClbTSKh66WfWC/fg77ZpSyc0ssQ964Z0RKXlVLprnMtschUU3gT49uI0BOa2ujnBOAHQwJN5N3vGVDfcNEth2jCcwxIgGpCTvqchbz4WEkolo5zRuS3imhfgG1K+Ura6h0NDhzkBIAl6GXLVmv+jFbcogzf31mSXS9Zauws6noR6DgkJnvvaTlc8CbcR68H5H+b3cEhCg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AM8P251CA0003.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:21b::8) by AS2PR08MB8383.eurprd08.prod.outlook.com (2603:10a6:20b:55a::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.21; Fri, 12 May 2023 09:39:09 +0000 Received: from AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:21b:cafe::a6) by AM8P251CA0003.outlook.office365.com (2603:10a6:20b:21b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT011.mail.protection.outlook.com (100.127.140.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.18 via Frontend Transport; Fri, 12 May 2023 09:39:09 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:38:58 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:38:57 +0000 Received: from e129018.arm.com (10.57.21.161) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 12 May 2023 09:38:57 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 08/26] arm: [MVE intrinsics] rework vqshluq Date: Fri, 12 May 2023 11:38:37 +0200 Message-ID: <20230512093855.79529-8-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512093855.79529-1-christophe.lyon@arm.com> References: <20230512093855.79529-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT011:EE_|AS2PR08MB8383:EE_|DBAEUR03FT025:EE_|DU2PR08MB10108:EE_ X-MS-Office365-Filtering-Correlation-Id: cd98ef82-e3af-4fcf-1905-08db52ccc2df x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Zo3Hn+InfXqt3T0d233a2df/oi9ifXW//6Px1Ds1CzQwOxpekDzUOVXL0cllK2adJoNsTUp5REUtTiB3RebwJ5ffi2PwUGntwQjqhfd8XE9NZ2v4pQSm44CqW4APygfqnEwPVpzMnWGRfhGUR4EpVO5eJR5RTruIqsOKHXj0DL2thcKIZ6RQdJTjlTpK+PaZ5zRi1vWKu8bhqOcpeUH5iNY9We4VqLDaIz5LYH3+HBWYZ7NkTGeYezxGhirDWjukP4LZPvNd2yOsItbl1QrIfwykB7yVCpXpgKZofziHmwipmCxFZOm9acJkU8Zc4w/oHK6yniI2oTM1ODkrQYgtHQTehh4tAr56Edkdo7x8DUri66UHEZwNh13eyxr1WgZGrOoP6cZEBSoCu1tIwqMSL4wxwvSgNWytN8q44KKWGzu82GyQ+tbJUXnYvwOJvZ8BBrw3rsbs4A1QTvNwWenatqzj9RxLfUBirV2YyC4V5C1wUx62mmqsJVlJ1GIKcBzpRsTkUqUZF6QamAc1XepaEHzZMl1ZDrJnNJN3+0UdpdrtEPTHiINss3w7gVdZOfiBsYw1cAtt3FOlD5PKrpDmbG0nNSYfMrT96b6f07mP1+xRyNnaKxGJ8b8fAKCMqkIQnxGexpBk81EGtH9TFVDk385LernwG6bxME6+ul8LeldPqdlp/traMcNF5P7on28vYsBOXM6oBmVrvTlkzA1T9Swf2chtvKxmTelGyFv2EYOr80k3RtBoAtFDam53PzDt X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199021)(36840700001)(46966006)(8936002)(8676002)(7696005)(5660300002)(82310400005)(110136005)(6636002)(36756003)(4326008)(82740400003)(70586007)(70206006)(40480700001)(316002)(478600001)(44832011)(41300700001)(356005)(81166007)(6666004)(36860700001)(336012)(2906002)(86362001)(4001150100001)(30864003)(2616005)(426003)(186003)(47076005)(83380400001)(1076003)(26005)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8383 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: afaaa04d-0139-4f7f-da5b-08db52ccbce5 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: igNmuhTQVRaKJEJwWlbQYD627EBWuBSIa1lfc6aT2ZvLTBsF0bLeWnbcN320ozplPnblu1K7roreaJm4GYTcL0gN041K5dZIvUKazGbOtMaN1MASFk+P/jCRRMAf0tHdiQt0U/OGzgGPk9Kgm9/O7LPfPA9nSxwXsNOPxev2zIRuqegIw9uusEmq2O8+YyrP2jEziXFnKYzUqzjT96ESQIXmDBWIpjYrZ1MVWl1xZki56lkYGYVi4wPrIZ8OOFoyBgQTRo8HkbdRtWRgnQow2WRvLL2wz6PAKRMip0KDjuhe7+E94s+x4o0oYPUUSxYzTOe48LdnyPw3WLEuoJPuV1JmPXWzWFKVBOYasZNpjXmJjhaPz/UWSZz09QuMZKc5atGpzL7twNIv5VNmNzW0K08eFYOe+uSVQ8q3I/BKo7t43ga1T4NVLpZgxHXFrKs0av3LYdm9MUoWUih4kcT2nvXECC9DEZ8d02up/8dQ+oCKXIv0eeyQTKG1mEf+B005IALUdKOKDpc/d5eIxBWrNEnJ/eHWTtRNxbZNX1vKKMEn818qrPBE8esdavZ0qo98g8kLJJv6+3z/Gul/rR6FMJjqfQrZpdDBmnoGLDAb9PmX0EaNFgJYl4umJmbXkeGMB2LawNSwidQ0rYkNKb6vVGKHv/T/iiI8rpTS/Z0OZVeEcr6ofkA4vU+08iufyIm/C6NIBT0Sal8qeKCR/dyUeQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(396003)(376002)(39860400002)(136003)(451199021)(40470700004)(46966006)(36840700001)(2906002)(4001150100001)(83380400001)(2616005)(186003)(81166007)(82740400003)(40480700001)(316002)(86362001)(41300700001)(30864003)(1076003)(26005)(336012)(47076005)(36860700001)(426003)(44832011)(5660300002)(110136005)(40460700003)(8936002)(8676002)(82310400005)(7696005)(478600001)(6666004)(70206006)(6636002)(36756003)(70586007)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 09:39:19.9107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd98ef82-e3af-4fcf-1905-08db52ccc2df X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB10108 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Implement vqshluq using the new MVE builtins framework. 2022-12-12 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vqshluq): New. * config/arm/arm-mve-builtins-base.def (vqshluq): New. * config/arm/arm-mve-builtins-base.h (vqshluq): New. * config/arm/arm_mve.h (vqshluq): Remove. (vqshluq_m): Remove. (vqshluq_n_s8): Remove. (vqshluq_n_s16): Remove. (vqshluq_n_s32): Remove. (vqshluq_m_n_s8): Remove. (vqshluq_m_n_s16): Remove. (vqshluq_m_n_s32): Remove. (__arm_vqshluq_n_s8): Remove. (__arm_vqshluq_n_s16): Remove. (__arm_vqshluq_n_s32): Remove. (__arm_vqshluq_m_n_s8): Remove. (__arm_vqshluq_m_n_s16): Remove. (__arm_vqshluq_m_n_s32): Remove. (__arm_vqshluq): Remove. (__arm_vqshluq_m): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 1 + gcc/config/arm/arm-mve-builtins-base.def | 1 + gcc/config/arm/arm-mve-builtins-base.h | 1 + gcc/config/arm/arm_mve.h | 111 ----------------------- 4 files changed, 3 insertions(+), 111 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index a2b227bb2aa..739ab604843 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -332,6 +332,7 @@ FUNCTION_WITHOUT_N_NO_U_F (vqnegq, VQNEGQ) FUNCTION_WITH_M_N_NO_F (vqrshlq, VQRSHLQ) FUNCTION_WITH_M_N_NO_U_F (vqrdmulhq, VQRDMULHQ) FUNCTION_WITH_M_N_R (vqshlq, VQSHLQ) +FUNCTION_ONLY_N_NO_U_F (vqshluq, VQSHLUQ) FUNCTION_ONLY_N_NO_F (vqrshrnbq, VQRSHRNBQ) FUNCTION_ONLY_N_NO_F (vqrshrntq, VQRSHRNTQ) FUNCTION_ONLY_N_NO_U_F (vqrshrunbq, VQRSHRUNBQ) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index c4ef74169dd..3f7bb414e40 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -106,6 +106,7 @@ DEF_MVE_FUNCTION (vqrshrunbq, binary_rshift_narrow_unsigned, signed_16_32, m_or_ DEF_MVE_FUNCTION (vqrshruntq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) DEF_MVE_FUNCTION (vqshlq, binary_lshift, all_integer, m_or_none) DEF_MVE_FUNCTION (vqshlq, binary_lshift_r, all_integer, m_or_none) +DEF_MVE_FUNCTION (vqshluq, binary_lshift_unsigned, all_signed, m_or_none) DEF_MVE_FUNCTION (vqshrnbq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vqshrntq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vqshrunbq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 41b2e19c2d7..797f8ba2f5e 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -118,6 +118,7 @@ extern const function_base *const vqrshrntq; extern const function_base *const vqrshrunbq; extern const function_base *const vqrshruntq; extern const function_base *const vqshlq; +extern const function_base *const vqshluq; extern const function_base *const vqshrnbq; extern const function_base *const vqshrntq; extern const function_base *const vqshrunbq; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index c995093e12f..673a3df1bfd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -50,7 +50,6 @@ #define vcaddq_rot270(__a, __b) __arm_vcaddq_rot270(__a, __b) #define vbicq(__a, __b) __arm_vbicq(__a, __b) #define vbrsrq(__a, __b) __arm_vbrsrq(__a, __b) -#define vqshluq(__a, __imm) __arm_vqshluq(__a, __imm) #define vhcaddq_rot90(__a, __b) __arm_vhcaddq_rot90(__a, __b) #define vhcaddq_rot270(__a, __b) __arm_vhcaddq_rot270(__a, __b) #define vmulltq_poly(__a, __b) __arm_vmulltq_poly(__a, __b) @@ -62,7 +61,6 @@ #define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm) #define vsliq(__a, __b, __imm) __arm_vsliq(__a, __b, __imm) #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) -#define vqshluq_m(__inactive, __a, __imm, __p) __arm_vqshluq_m(__inactive, __a, __imm, __p) #define vbicq_m(__inactive, __a, __b, __p) __arm_vbicq_m(__inactive, __a, __b, __p) #define vbrsrq_m(__inactive, __a, __b, __p) __arm_vbrsrq_m(__inactive, __a, __b, __p) #define vcaddq_rot270_m(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m(__inactive, __a, __b, __p) @@ -284,7 +282,6 @@ #define vcaddq_rot270_u8(__a, __b) __arm_vcaddq_rot270_u8(__a, __b) #define vbicq_u8(__a, __b) __arm_vbicq_u8(__a, __b) #define vbrsrq_n_u8(__a, __b) __arm_vbrsrq_n_u8(__a, __b) -#define vqshluq_n_s8(__a, __imm) __arm_vqshluq_n_s8(__a, __imm) #define vornq_s8(__a, __b) __arm_vornq_s8(__a, __b) #define vmulltq_int_s8(__a, __b) __arm_vmulltq_int_s8(__a, __b) #define vmullbq_int_s8(__a, __b) __arm_vmullbq_int_s8(__a, __b) @@ -301,7 +298,6 @@ #define vcaddq_rot270_u16(__a, __b) __arm_vcaddq_rot270_u16(__a, __b) #define vbicq_u16(__a, __b) __arm_vbicq_u16(__a, __b) #define vbrsrq_n_u16(__a, __b) __arm_vbrsrq_n_u16(__a, __b) -#define vqshluq_n_s16(__a, __imm) __arm_vqshluq_n_s16(__a, __imm) #define vornq_s16(__a, __b) __arm_vornq_s16(__a, __b) #define vmulltq_int_s16(__a, __b) __arm_vmulltq_int_s16(__a, __b) #define vmullbq_int_s16(__a, __b) __arm_vmullbq_int_s16(__a, __b) @@ -318,7 +314,6 @@ #define vcaddq_rot270_u32(__a, __b) __arm_vcaddq_rot270_u32(__a, __b) #define vbicq_u32(__a, __b) __arm_vbicq_u32(__a, __b) #define vbrsrq_n_u32(__a, __b) __arm_vbrsrq_n_u32(__a, __b) -#define vqshluq_n_s32(__a, __imm) __arm_vqshluq_n_s32(__a, __imm) #define vornq_s32(__a, __b) __arm_vornq_s32(__a, __b) #define vmulltq_int_s32(__a, __b) __arm_vmulltq_int_s32(__a, __b) #define vmullbq_int_s32(__a, __b) __arm_vmullbq_int_s32(__a, __b) @@ -446,16 +441,13 @@ #define vcvtq_m_u32_f32(__inactive, __a, __p) __arm_vcvtq_m_u32_f32(__inactive, __a, __p) #define vsriq_m_n_s8(__a, __b, __imm, __p) __arm_vsriq_m_n_s8(__a, __b, __imm, __p) #define vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) -#define vqshluq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s8(__inactive, __a, __imm, __p) #define vsriq_m_n_u8(__a, __b, __imm, __p) __arm_vsriq_m_n_u8(__a, __b, __imm, __p) #define vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) #define vsriq_m_n_s16(__a, __b, __imm, __p) __arm_vsriq_m_n_s16(__a, __b, __imm, __p) #define vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) -#define vqshluq_m_n_s16(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s16(__inactive, __a, __imm, __p) #define vsriq_m_n_u16(__a, __b, __imm, __p) __arm_vsriq_m_n_u16(__a, __b, __imm, __p) #define vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) #define vsriq_m_n_s32(__a, __b, __imm, __p) __arm_vsriq_m_n_s32(__a, __b, __imm, __p) -#define vqshluq_m_n_s32(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s32(__inactive, __a, __imm, __p) #define vsriq_m_n_u32(__a, __b, __imm, __p) __arm_vsriq_m_n_u32(__a, __b, __imm, __p) #define vbicq_m_s8(__inactive, __a, __b, __p) __arm_vbicq_m_s8(__inactive, __a, __b, __p) #define vbicq_m_s32(__inactive, __a, __b, __p) __arm_vbicq_m_s32(__inactive, __a, __b, __p) @@ -1287,13 +1279,6 @@ __arm_vbrsrq_n_u8 (uint8x16_t __a, int32_t __b) return __builtin_mve_vbrsrq_n_uv16qi (__a, __b); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_n_s8 (int8x16_t __a, const int __imm) -{ - return __builtin_mve_vqshluq_n_sv16qi (__a, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq_s8 (int8x16_t __a, int8x16_t __b) @@ -1408,13 +1393,6 @@ __arm_vbrsrq_n_u16 (uint16x8_t __a, int32_t __b) return __builtin_mve_vbrsrq_n_uv8hi (__a, __b); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_n_s16 (int16x8_t __a, const int __imm) -{ - return __builtin_mve_vqshluq_n_sv8hi (__a, __imm); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq_s16 (int16x8_t __a, int16x8_t __b) @@ -1529,13 +1507,6 @@ __arm_vbrsrq_n_u32 (uint32x4_t __a, int32_t __b) return __builtin_mve_vbrsrq_n_uv4si (__a, __b); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_n_s32 (int32x4_t __a, const int __imm) -{ - return __builtin_mve_vqshluq_n_sv4si (__a, __imm); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq_s32 (int32x4_t __a, int32x4_t __b) @@ -1982,13 +1953,6 @@ __arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t return __builtin_mve_vsriq_m_n_sv16qi (__a, __b, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m_n_s8 (uint8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshluq_m_n_sv16qi (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) @@ -2003,13 +1967,6 @@ __arm_vsriq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t return __builtin_mve_vsriq_m_n_sv8hi (__a, __b, __imm, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m_n_s16 (uint16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshluq_m_n_sv8hi (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) @@ -2024,13 +1981,6 @@ __arm_vsriq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t return __builtin_mve_vsriq_m_n_sv4si (__a, __b, __imm, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m_n_s32 (uint32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshluq_m_n_sv4si (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) @@ -7377,13 +7327,6 @@ __arm_vbrsrq (uint8x16_t __a, int32_t __b) return __arm_vbrsrq_n_u8 (__a, __b); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq (int8x16_t __a, const int __imm) -{ - return __arm_vqshluq_n_s8 (__a, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq (int8x16_t __a, int8x16_t __b) @@ -7496,13 +7439,6 @@ __arm_vbrsrq (uint16x8_t __a, int32_t __b) return __arm_vbrsrq_n_u16 (__a, __b); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq (int16x8_t __a, const int __imm) -{ - return __arm_vqshluq_n_s16 (__a, __imm); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq (int16x8_t __a, int16x8_t __b) @@ -7615,13 +7551,6 @@ __arm_vbrsrq (uint32x4_t __a, int32_t __b) return __arm_vbrsrq_n_u32 (__a, __b); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq (int32x4_t __a, const int __imm) -{ - return __arm_vqshluq_n_s32 (__a, __imm); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq (int32x4_t __a, int32x4_t __b) @@ -8028,13 +7957,6 @@ __arm_vsriq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) return __arm_vsriq_m_n_s8 (__a, __b, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m (uint8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshluq_m_n_s8 (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) @@ -8049,13 +7971,6 @@ __arm_vsriq_m (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) return __arm_vsriq_m_n_s16 (__a, __b, __imm, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m (uint16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshluq_m_n_s16 (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) @@ -8070,13 +7985,6 @@ __arm_vsriq_m (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) return __arm_vsriq_m_n_s32 (__a, __b, __imm, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshluq_m (uint32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshluq_m_n_s32 (__inactive, __a, __imm, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) @@ -12553,12 +12461,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) -#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) - #define __arm_vmulltq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -13383,12 +13285,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) -#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) - #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -14161,13 +14057,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) -#define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshluq_m_n_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshluq_m_n_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshluq_m_n_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) - #define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \