From patchwork Fri May 12 09:38:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 69227 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0A978388F37C for ; Fri, 12 May 2023 09:43:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0A978388F37C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683884584; bh=8O654RhzKW6JztNmUZojxEpLIIubqIiQRAhOExeh/Xo=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=j8VWGVv3tR/AY5xAbpQXWj5ENb6ApcdKeI8wfqA+6dd6Cq//0Ss568t/N+a3uLM/6 24VVQFnJH5iVR6pJHepubFoZNQX/AuWsDioEqVtVLcf1tosuHYpxMp1Fs86UYsS6cc G9joMhphR3twIR4z0QTGuNe0Sa64TBwVogld7wGo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2069.outbound.protection.outlook.com [40.107.104.69]) by sourceware.org (Postfix) with ESMTPS id 3BFE638555BA for ; Fri, 12 May 2023 09:39:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3BFE638555BA Received: from DUZPR01CA0053.eurprd01.prod.exchangelabs.com (2603:10a6:10:469::11) by PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23; Fri, 12 May 2023 09:39:25 +0000 Received: from DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:469:cafe::f1) by DUZPR01CA0053.outlook.office365.com (2603:10a6:10:469::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT061.mail.protection.outlook.com (100.127.143.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.22 via Frontend Transport; Fri, 12 May 2023 09:39:25 +0000 Received: ("Tessian outbound 3a01b65b5aad:v136"); Fri, 12 May 2023 09:39:25 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 17110e48c779627b X-CR-MTA-TID: 64aa7808 Received: from 04e8ea24944e.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id DF2FE2D9-0E34-4FF7-9CF2-56FDE26B161F.1; Fri, 12 May 2023 09:39:19 +0000 Received: from EUR01-DB5-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 04e8ea24944e.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 12 May 2023 09:39:19 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jFVpLt5yW9/HQ6WA5Mx7pIYOOZKpAY2SEOqbQ42NwY6+WyO7NVfR34wgGEHmjhTOjBYP5u+gp1O+RjukMGDaF7ZfdLWIPoFSuO14l+gBo7qW/dmFMLFUB6v6thhhPjuBVcLI+S1LX2TgbOIprCE6bT2iXrOQSHG+6+W+Ukxi8+ODfbb2SxIEvKVgQyua2dulsXycBu1SsHvE03f1csqU7DYVjHKeDi/k6oKHAVWtXkNMbWpkucwuICKprERjjFFhAiiKwIjhraXd8Vudk1rd2mRiQu4iInwZ3+p8dJxAIZZ57N1g+fznI8x4IM7LD8bvwmmJGUrIG0f1WuVHuhOFKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8O654RhzKW6JztNmUZojxEpLIIubqIiQRAhOExeh/Xo=; b=Ak1gltWU5y1vRJZS9HuRLxCvnaNsx7/zU81jU5WTy/N+nDy2Ge/MNrv5bHd8W7nsgWMTuk8H5423InO3y6OuT2HCoinFZBtCwtyijZuaSNRq6s0P77DtqB5vdGE3uTcBGoUffus05VF0O8Idy0ie3AIctLmlpugiTq5ofmIPwgwphLyBgpCoDqFgxrsmq828UBpqRqI8vS5Cb3VvSwxo1A3Gz1i/XhssLixT09viGVCLpi1ucxlQORpPnak4w4xkZ9IW26JBvEmjZzKzZ2RidDv8p3wd8YwGoGkzQJRIOc5JQVn+1TAdHROyIjJOVbOmZoEvn57bowWmFCUMIDXBJA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AS9PR06CA0463.eurprd06.prod.outlook.com (2603:10a6:20b:49a::14) by AM8PR08MB5761.eurprd08.prod.outlook.com (2603:10a6:20b:1d0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23; Fri, 12 May 2023 09:39:15 +0000 Received: from AM7EUR03FT039.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:49a:cafe::d9) by AS9PR06CA0463.outlook.office365.com (2603:10a6:20b:49a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT039.mail.protection.outlook.com (100.127.140.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:15 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:39:03 +0000 Received: from e129018.arm.com (10.57.21.161) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 12 May 2023 09:39:03 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 23/26] arm: [MVE intrinsics] rework vsliq Date: Fri, 12 May 2023 11:38:52 +0200 Message-ID: <20230512093855.79529-23-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512093855.79529-1-christophe.lyon@arm.com> References: <20230512093855.79529-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT039:EE_|AM8PR08MB5761:EE_|DBAEUR03FT061:EE_|PA4PR08MB5902:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ae67444-d534-471b-8399-08db52ccc65c x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Vn4gMT98gUFdMbrw1NFDnBopni6fRg0FW/uu2nLjM4xfq4gUuxgMdU6Ku3ZjdYok27gONelAsMJ1P8/yci9Ggdt0xikakvujm7ptSQWMPk06++gaz8xFiOk5vIHfx6bPZjHTRSk6gQpcB+hhoiUAzAWdn4JHQWC+fDr0UyFo0e1nR0F0ZvSwP7CRYqeghncbUcmGLaM868H66NtzB7xdbfOW4CzZl3gepu1NNOa2OR/s1Rlbz+Wx/SUR5UudqShgbXF5mEggQENg8l6j2exMSpp6sU96K+wdmvO1ZFNH4Ajzz1uCSKj+ZrwhUZplnvB5FxYNg4FuRMU38qcT4gsvID9FSaD7eegKuwHovC/YWYoVhsztvWLefjD0m+MrIwCYUWtx/93HDp3jbR0zLjh7chmCHQVU/vOMNbZXlVO+442ofb6jb8i7UVMHOcEQY5PFJtkV/XAsJXoMdTrXo/f7h+rSh7vqMYP/Z1/cRvKSYp1AVTGU//ye8wdZK/3GchrinLQc4z29PZ7GNAKMlKTlMWPoGS0Z2BR9jcmbfJWsxx6hOkGx8nmiOieq2XKH2jZ6IpTalekk2a0XkTCxl/2Qg8LdUEjY8beOJODY6dN/8zycVSetzMi8bxnL6Mxwy+xjWZEGO6oTYKwXhAiepSttUeyzRQh0GyGie9nEWDSlGBfJ1WI78X70Iv5oEu89nUc+SDeRzWwJvIF0kyGtEnlZW7BTzjhcuBPXE0VUL+Q7ngWlTFvnwBV4mJLfvnrLydDeSo8fkLbzCJXkZQtkdynU/g== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(41300700001)(7696005)(6666004)(5660300002)(83380400001)(6636002)(4326008)(44832011)(86362001)(316002)(82310400005)(8936002)(36756003)(8676002)(47076005)(2616005)(426003)(4001150100001)(336012)(30864003)(82740400003)(110136005)(2906002)(40480700001)(70206006)(36860700001)(70586007)(1076003)(40460700003)(186003)(26005)(81166007)(356005)(478600001)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5761 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: ceaa31d4-aac7-4c7e-bc08-08db52ccc042 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TEV9H12kFI+3esqm2TLxujR5wQjv1AIwGS+zqWc9Z0xBG2ssgD6wNHgd1GuvddqrQabb5wiPO/AqTmiM/ZA0sCB2l1/TTzwP/9AbYHAnYEAOE6xRKbbrI3Q0yK0sy9WJ7Z+Wb3LiDrUEkDg++PmncYZDVKrNcmv6X0sEjzI9aXkisTgemR5nicQuuaNrbC7AkuMstMf8kfDiFLJYpJHuooV4+t334C6rJP8Nl2iHFEsWm5WwRNZHOoplHBw1Fd2NJvcO9J4RiviQR6K2qG3j1zQKj88+cCcVjwC/UH56JKVn7WIpNNp2GCyiINQB233pioH8qVK28oNHKYQMD312o+3JfB/FmHsNgO4kZZ0nFbOC0k8USMU6nc9ql/+vfnjfN2KYhs1tEJnLftvM2XMvz643EfpoCeXu+jtNy4sKtykMey1FWLYCBHnci+Dp5RjxkwrKho29RTvb+kZWmaovylfDtAV0Ew8hYsX41kItZoh7D2/RGCiiIQmYz1Sy/39M74VOb8loEyY93rYFXVGG2jfaaE5Xsb4EwY0Y7Bx10Ogqalgqe8g0V7AhFekpbsyKq8svH1BzQzslS7aysWEZraW61YRduBA44wjmkjWv2/KmMw8/kok9RBmSFWG1uzzPH9ip9DwtqjI/9rLEHTSem8aebH+l4ucX/9i+ArW6rzTtih6tYqeHl2k1sQtyl2Zh5CEwZT+5KjHZr3/JMij6bz1n123NHGELL+Y4cLZmqakmyCoALO41mYDaLumBMKoy X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199021)(40470700004)(46966006)(36840700001)(6636002)(82740400003)(426003)(336012)(81166007)(26005)(83380400001)(40480700001)(1076003)(2616005)(186003)(47076005)(36860700001)(2906002)(30864003)(4001150100001)(8676002)(44832011)(5660300002)(8936002)(36756003)(478600001)(40460700003)(110136005)(7696005)(6666004)(41300700001)(316002)(86362001)(70586007)(4326008)(70206006)(82310400005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 09:39:25.7658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ae67444-d534-471b-8399-08db52ccc65c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB5902 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Implement vsliq using the new MVE builtins framework. 2022-12-12 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vsliq): New. * config/arm/arm-mve-builtins-base.def (vsliq): New. * config/arm/arm-mve-builtins-base.h (vsliq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vsliq. * config/arm/arm_mve.h (vsliq): Remove. (vsliq_m): Remove. (vsliq_n_u8): Remove. (vsliq_n_s8): Remove. (vsliq_n_u16): Remove. (vsliq_n_s16): Remove. (vsliq_n_u32): Remove. (vsliq_n_s32): Remove. (vsliq_m_n_s8): Remove. (vsliq_m_n_s32): Remove. (vsliq_m_n_s16): Remove. (vsliq_m_n_u8): Remove. (vsliq_m_n_u32): Remove. (vsliq_m_n_u16): Remove. (__arm_vsliq_n_u8): Remove. (__arm_vsliq_n_s8): Remove. (__arm_vsliq_n_u16): Remove. (__arm_vsliq_n_s16): Remove. (__arm_vsliq_n_u32): Remove. (__arm_vsliq_n_s32): Remove. (__arm_vsliq_m_n_s8): Remove. (__arm_vsliq_m_n_s32): Remove. (__arm_vsliq_m_n_s16): Remove. (__arm_vsliq_m_n_u8): Remove. (__arm_vsliq_m_n_u32): Remove. (__arm_vsliq_m_n_u16): Remove. (__arm_vsliq): Remove. (__arm_vsliq_m): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 1 + gcc/config/arm/arm-mve-builtins-base.def | 1 + gcc/config/arm/arm-mve-builtins-base.h | 1 + gcc/config/arm/arm-mve-builtins.cc | 3 +- gcc/config/arm/arm_mve.h | 212 ----------------------- 5 files changed, 5 insertions(+), 213 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index b1440ca489e..873c7d365f3 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -387,6 +387,7 @@ FUNCTION_WITH_M_N_R (vshlq, VSHLQ) FUNCTION_ONLY_N_NO_F (vshrnbq, VSHRNBQ) FUNCTION_ONLY_N_NO_F (vshrntq, VSHRNTQ) FUNCTION_ONLY_N_NO_F (vshrq, VSHRQ) +FUNCTION_ONLY_N_NO_F (vsliq, VSLIQ) FUNCTION_WITH_RTX_M_N (vsubq, MINUS, VSUBQ) FUNCTION (vuninitializedq, vuninitializedq_impl,) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index de4c473f618..2d1b87b90c3 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -140,6 +140,7 @@ DEF_MVE_FUNCTION (vshlq, binary_lshift_r, all_integer, m_or_none) // "_r" forms DEF_MVE_FUNCTION (vshrnbq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vshrntq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vshrq, binary_rshift, all_integer, mx_or_none) +DEF_MVE_FUNCTION (vsliq, ternary_lshift, all_integer, m_or_none) DEF_MVE_FUNCTION (vsubq, binary_opt_n, all_integer, mx_or_none) DEF_MVE_FUNCTION (vuninitializedq, inherent, all_integer_with_64, none) #undef REQUIRES_FLOAT diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index ec5b4fbffb9..84fff0f6d0e 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -160,6 +160,7 @@ extern const function_base *const vshlq; extern const function_base *const vshrnbq; extern const function_base *const vshrntq; extern const function_base *const vshrq; +extern const function_base *const vsliq; extern const function_base *const vsubq; extern const function_base *const vuninitializedq; diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc index 87fcbc31f2f..f5056bdd1bb 100644 --- a/gcc/config/arm/arm-mve-builtins.cc +++ b/gcc/config/arm/arm-mve-builtins.cc @@ -719,7 +719,8 @@ function_instance::has_inactive_argument () const || base == functions::vrshrnbq || base == functions::vrshrntq || base == functions::vshrnbq - || base == functions::vshrntq) + || base == functions::vshrntq + || base == functions::vsliq) return false; return true; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 72b50764963..72177f9c53e 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -55,7 +55,6 @@ #define vbicq_m_n(__a, __imm, __p) __arm_vbicq_m_n(__a, __imm, __p) #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) #define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm) -#define vsliq(__a, __b, __imm) __arm_vsliq(__a, __b, __imm) #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) #define vbicq_m(__inactive, __a, __b, __p) __arm_vbicq_m(__inactive, __a, __b, __p) #define vcaddq_rot270_m(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m(__inactive, __a, __b, __p) @@ -65,7 +64,6 @@ #define vmullbq_int_m(__inactive, __a, __b, __p) __arm_vmullbq_int_m(__inactive, __a, __b, __p) #define vmulltq_int_m(__inactive, __a, __b, __p) __arm_vmulltq_int_m(__inactive, __a, __b, __p) #define vornq_m(__inactive, __a, __b, __p) __arm_vornq_m(__inactive, __a, __b, __p) -#define vsliq_m(__a, __b, __imm, __p) __arm_vsliq_m(__a, __b, __imm, __p) #define vmullbq_poly_m(__inactive, __a, __b, __p) __arm_vmullbq_poly_m(__inactive, __a, __b, __p) #define vmulltq_poly_m(__inactive, __a, __b, __p) __arm_vmulltq_poly_m(__inactive, __a, __b, __p) #define vstrbq_scatter_offset(__base, __offset, __value) __arm_vstrbq_scatter_offset(__base, __offset, __value) @@ -341,17 +339,11 @@ #define vshlcq_s32(__a, __b, __imm) __arm_vshlcq_s32(__a, __b, __imm) #define vshlcq_u32(__a, __b, __imm) __arm_vshlcq_u32(__a, __b, __imm) #define vsriq_n_u8(__a, __b, __imm) __arm_vsriq_n_u8(__a, __b, __imm) -#define vsliq_n_u8(__a, __b, __imm) __arm_vsliq_n_u8(__a, __b, __imm) #define vsriq_n_s8(__a, __b, __imm) __arm_vsriq_n_s8(__a, __b, __imm) -#define vsliq_n_s8(__a, __b, __imm) __arm_vsliq_n_s8(__a, __b, __imm) #define vsriq_n_u16(__a, __b, __imm) __arm_vsriq_n_u16(__a, __b, __imm) -#define vsliq_n_u16(__a, __b, __imm) __arm_vsliq_n_u16(__a, __b, __imm) #define vsriq_n_s16(__a, __b, __imm) __arm_vsriq_n_s16(__a, __b, __imm) -#define vsliq_n_s16(__a, __b, __imm) __arm_vsliq_n_s16(__a, __b, __imm) #define vsriq_n_u32(__a, __b, __imm) __arm_vsriq_n_u32(__a, __b, __imm) -#define vsliq_n_u32(__a, __b, __imm) __arm_vsliq_n_u32(__a, __b, __imm) #define vsriq_n_s32(__a, __b, __imm) __arm_vsriq_n_s32(__a, __b, __imm) -#define vsliq_n_s32(__a, __b, __imm) __arm_vsliq_n_s32(__a, __b, __imm) #define vcvtbq_m_f16_f32(__a, __b, __p) __arm_vcvtbq_m_f16_f32(__a, __b, __p) #define vcvtbq_m_f32_f16(__inactive, __a, __p) __arm_vcvtbq_m_f32_f16(__inactive, __a, __p) #define vcvttq_m_f16_f32(__a, __b, __p) __arm_vcvttq_m_f16_f32(__a, __b, __p) @@ -432,12 +424,6 @@ #define vornq_m_u8(__inactive, __a, __b, __p) __arm_vornq_m_u8(__inactive, __a, __b, __p) #define vornq_m_u32(__inactive, __a, __b, __p) __arm_vornq_m_u32(__inactive, __a, __b, __p) #define vornq_m_u16(__inactive, __a, __b, __p) __arm_vornq_m_u16(__inactive, __a, __b, __p) -#define vsliq_m_n_s8(__a, __b, __imm, __p) __arm_vsliq_m_n_s8(__a, __b, __imm, __p) -#define vsliq_m_n_s32(__a, __b, __imm, __p) __arm_vsliq_m_n_s32(__a, __b, __imm, __p) -#define vsliq_m_n_s16(__a, __b, __imm, __p) __arm_vsliq_m_n_s16(__a, __b, __imm, __p) -#define vsliq_m_n_u8(__a, __b, __imm, __p) __arm_vsliq_m_n_u8(__a, __b, __imm, __p) -#define vsliq_m_n_u32(__a, __b, __imm, __p) __arm_vsliq_m_n_u32(__a, __b, __imm, __p) -#define vsliq_m_n_u16(__a, __b, __imm, __p) __arm_vsliq_m_n_u16(__a, __b, __imm, __p) #define vmullbq_poly_m_p8(__inactive, __a, __b, __p) __arm_vmullbq_poly_m_p8(__inactive, __a, __b, __p) #define vmullbq_poly_m_p16(__inactive, __a, __b, __p) __arm_vmullbq_poly_m_p16(__inactive, __a, __b, __p) #define vmulltq_poly_m_p8(__inactive, __a, __b, __p) __arm_vmulltq_poly_m_p8(__inactive, __a, __b, __p) @@ -1538,13 +1524,6 @@ __arm_vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) return __builtin_mve_vsriq_n_uv16qi (__a, __b, __imm); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) @@ -1552,13 +1531,6 @@ __arm_vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) return __builtin_mve_vsriq_n_sv16qi (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_sv16qi (__a, __b, __imm); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) @@ -1566,13 +1538,6 @@ __arm_vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) return __builtin_mve_vsriq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) @@ -1580,13 +1545,6 @@ __arm_vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) return __builtin_mve_vsriq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_sv8hi (__a, __b, __imm); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) @@ -1594,13 +1552,6 @@ __arm_vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) return __builtin_mve_vsriq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) @@ -1608,13 +1559,6 @@ __arm_vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) return __builtin_mve_vsriq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vsliq_n_sv4si (__a, __b, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -1951,48 +1895,6 @@ __arm_vornq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pr return __builtin_mve_vornq_m_uv8hi (__inactive, __a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_sv16qi (__a, __b, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_sv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_uv16qi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_uv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsliq_m_n_uv8hi (__a, __b, __imm, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmullbq_poly_m_p8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) @@ -7010,13 +6912,6 @@ __arm_vsriq (uint8x16_t __a, uint8x16_t __b, const int __imm) return __arm_vsriq_n_u8 (__a, __b, __imm); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (uint8x16_t __a, uint8x16_t __b, const int __imm) -{ - return __arm_vsliq_n_u8 (__a, __b, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int8x16_t __a, int8x16_t __b, const int __imm) @@ -7024,13 +6919,6 @@ __arm_vsriq (int8x16_t __a, int8x16_t __b, const int __imm) return __arm_vsriq_n_s8 (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (int8x16_t __a, int8x16_t __b, const int __imm) -{ - return __arm_vsliq_n_s8 (__a, __b, __imm); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (uint16x8_t __a, uint16x8_t __b, const int __imm) @@ -7038,13 +6926,6 @@ __arm_vsriq (uint16x8_t __a, uint16x8_t __b, const int __imm) return __arm_vsriq_n_u16 (__a, __b, __imm); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (uint16x8_t __a, uint16x8_t __b, const int __imm) -{ - return __arm_vsliq_n_u16 (__a, __b, __imm); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int16x8_t __a, int16x8_t __b, const int __imm) @@ -7052,13 +6933,6 @@ __arm_vsriq (int16x8_t __a, int16x8_t __b, const int __imm) return __arm_vsriq_n_s16 (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (int16x8_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vsliq_n_s16 (__a, __b, __imm); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (uint32x4_t __a, uint32x4_t __b, const int __imm) @@ -7066,13 +6940,6 @@ __arm_vsriq (uint32x4_t __a, uint32x4_t __b, const int __imm) return __arm_vsriq_n_u32 (__a, __b, __imm); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (uint32x4_t __a, uint32x4_t __b, const int __imm) -{ - return __arm_vsliq_n_u32 (__a, __b, __imm); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int32x4_t __a, int32x4_t __b, const int __imm) @@ -7080,13 +6947,6 @@ __arm_vsriq (int32x4_t __a, int32x4_t __b, const int __imm) return __arm_vsriq_n_s32 (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq (int32x4_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vsliq_n_s32 (__a, __b, __imm); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -7423,48 +7283,6 @@ __arm_vornq_m (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16 return __arm_vornq_m_u16 (__inactive, __a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_s8 (__a, __b, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_s16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_u8 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_u32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsliq_m (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsliq_m_n_u16 (__a, __b, __imm, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmullbq_poly_m (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) @@ -11356,16 +11174,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -12122,16 +11930,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -12714,16 +12512,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define __arm_vsliq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - #define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \