From patchwork Fri May 12 09:38:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 69234 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4BDB838AA256 for ; Fri, 12 May 2023 09:44:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4BDB838AA256 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683884674; bh=Q0WH79OJKcIR8YDXsy2n/5CeAuKDG7SA3fxfH15K1W8=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=II7ygBq0EiBeQZcS2C4ioVd/J8FXWctsSff18JjWuXoEw9ErnR2iFts9AyFuHj80w obGDvYjO5908VwCSCcFSNJA/A0BzHvgxSeB39jReYub3JShcOvrF4AYZEYV306j87g Ew8ZBTP8bBM4IO7wVtZ9f2QCPAd+jGh/4eJQ0CuM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2057.outbound.protection.outlook.com [40.107.6.57]) by sourceware.org (Postfix) with ESMTPS id 0BE2F3854176 for ; Fri, 12 May 2023 09:39:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0BE2F3854176 Received: from AS9PR06CA0403.eurprd06.prod.outlook.com (2603:10a6:20b:461::33) by AS4PR08MB7854.eurprd08.prod.outlook.com (2603:10a6:20b:51d::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.22; Fri, 12 May 2023 09:39:22 +0000 Received: from AM7EUR03FT045.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:461:cafe::47) by AS9PR06CA0403.outlook.office365.com (2603:10a6:20b:461::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT045.mail.protection.outlook.com (100.127.140.150) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23 via Frontend Transport; Fri, 12 May 2023 09:39:22 +0000 Received: ("Tessian outbound 945aec65ec65:v136"); Fri, 12 May 2023 09:39:21 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 695ca8aefa1e1e91 X-CR-MTA-TID: 64aa7808 Received: from 4234c5edbe00.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 258F4035-9773-4155-B9D1-6643562B46DA.1; Fri, 12 May 2023 09:39:15 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 4234c5edbe00.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 12 May 2023 09:39:15 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nOkrRizw8CZosGmm8EdR8CgAbHhhzS8ckV/+aFOoIZ77lEjsGluVRDj1UQxYPE9LJhKWyxiYgSoNe+wigWdKRMG4L6qUD/T3zVhoJTYHRPgygTUQKMN1LdytL8BM4m8GDoN+46y5B5hwrv1wRjALTiD0s6DhNpFU8NZlTOWI5APMRhyTazBcZeVVbwcsQ0TkFACrWMI5LxWN/we9GjT48wAD3L7WFnyiZDVaS2ysSHyNre6H+3fJDQfs41hw8d4nM69RK1PvDyH/svDS0WfPlF9W7JiW4uMMgmEx6eW0sqbpy4GStu/6rn0Q19cMBLOjXmv1OlUvXNRrLBqUercv4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Q0WH79OJKcIR8YDXsy2n/5CeAuKDG7SA3fxfH15K1W8=; b=aMCFt8zEhvgl6ApVTiZhkHXH+3dunOB7FqcenhvPTIMJ830r8GWpXmip5AYqadZy2Tz8H4MP+IvwKUHdt+lWum2NdW0fCcuRZHqcUC7zS68LG8wceL9VvHwNf1KmF/ZzMTb+Iu9LOQ7JX8kQ59ocfg+Q0icrfyETapqytoHRShFxcxNQ0ZFs6/YPERmXxyLeGRHZYjAGplX9Qv/ixm6EIgOecccQlq8Zo79xxG/DWtthzDsUpJS53PMrDhMarbNlNQT1hIS1oFQ/2wFeyEZcAkLQc+ySG0bqcGMgTZ8/FF5vWAFU0BeAlcxS0pCE4InF0sQ8jZL+oRL1HHixjQ8dKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AM0PR06CA0096.eurprd06.prod.outlook.com (2603:10a6:208:fa::37) by AS8PR08MB6152.eurprd08.prod.outlook.com (2603:10a6:20b:298::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.21; Fri, 12 May 2023 09:39:11 +0000 Received: from AM7EUR03FT006.eop-EUR03.prod.protection.outlook.com (2603:10a6:208:fa:cafe::e0) by AM0PR06CA0096.outlook.office365.com (2603:10a6:208:fa::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23 via Frontend Transport; Fri, 12 May 2023 09:39:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT006.mail.protection.outlook.com (100.127.141.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.22 via Frontend Transport; Fri, 12 May 2023 09:39:11 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:39:00 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:39:00 +0000 Received: from e129018.arm.com (10.57.21.161) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 12 May 2023 09:39:00 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 14/26] arm: [MVE intrinsics] rework vmvnq Date: Fri, 12 May 2023 11:38:43 +0200 Message-ID: <20230512093855.79529-14-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512093855.79529-1-christophe.lyon@arm.com> References: <20230512093855.79529-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT006:EE_|AS8PR08MB6152:EE_|AM7EUR03FT045:EE_|AS4PR08MB7854:EE_ X-MS-Office365-Filtering-Correlation-Id: 66f3ce57-9479-40b4-6669-08db52ccc42d x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: b+GYm7iU4EjSt6DHWO4Bl+KaOYeL6wEfPj323eQ27PB+7BU3jiRA05UXFkJ2rnGl1RGPD8+luo3X+h6Pgu1c8K6NCjrLKxV6mw8iVrRc4auCUbQ8Nqg/ORbqKVQa4vLsubiFKL//MQ8/UmRvBSwYJHzHsRAMMXxD8eRgt5neNgFj3Jx0CK1eMezITefvA/+gTOATrgRs4m+9JUNXV3E4MvO4bGOq7XC3PFdLi8nq42YrKNSldqqvZYbE5EtTQ7B0aZm0ht0IjhIcKVeRGOhQpJ8T8QbI3VSJ1QXI9MG9K9ahiiLnY3cYobVuW0WN5Sqi047tgxCxTODYw/61rZ1sRHnTsNnAFmVYxTJdfh98PBfsNYKixfGAvpCZ5eEbV0q8k83PCfq/OO2GPsTkZCOR90HQJBZJrHJgw4pNIquqSoMMT+Vx40HpE9DbII7dFaXLU2YbT7bFETa+LIWlyOWhY/vRbZ4ZSlk5NbHyMCmgwk1qpv1QWWN6WF40MoHx2zcUGC0aN/rup+kubx7LqvE9taphYrr7stQz5GknMdD1Ap7zSRBsjbPWxmUD6ZNlqb0gI13gDm5ne1vGr0D9+ly4GtOnerGhx7//rB4VHp9pKQCt0/8BsL+uzzAhvmslPzN9haR5332odBwseqcYySHEL8Rql2EvTIFaknRanAIJYA6QOUfpTpCBDaItTwW4nfVbMJUoTGHn//1xMuXNzxJlEUnhU1Q7bkJKqViFa5t1SAZaIDJ5n8t7HVcJwU4mJLNisTGIOF3xKx/cHZZCTZL/AA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199021)(46966006)(36840700001)(6666004)(7696005)(86362001)(36860700001)(83380400001)(1076003)(186003)(2616005)(47076005)(336012)(40480700001)(36756003)(426003)(82740400003)(82310400005)(356005)(81166007)(26005)(30864003)(2906002)(6636002)(4326008)(70206006)(70586007)(316002)(8936002)(8676002)(41300700001)(4001150100001)(5660300002)(44832011)(110136005)(478600001)(17423001)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6152 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 7285a071-f7e4-4045-28d2-08db52ccbdf8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FeYwIkxGwpAAXKwCnrNnIvzaJc76AJXLQlxhOl5VqCUtTCm7Bqr6k0JXDO898pzWDd1VpZUm7IqrhxROW7LT0uVNmMUkcQCkyS59kGDRaBHD44ntPfY1hPfVyNhujcM2gkBx8CsKXFkXCz5TOPN+A1RI/+GYre6zWkXMoIeGqH3S9poLcZ0NHIGQAvp7hAdzV7QnhLKAmA0nFiTZ/5tkzObdHCpPVN/R+si3/xSVrFPDlCpWgb1OUON8y0rhvnPSzt0v9cjo3uqQPT2rXjn9uqR6L0I/srYBhu2ZRlYedb+BEeoy+iME6lOUa3zvg2ZhdAxOtiLErn5aabnazwUcx0KsvfaDvxvBZ0BmgB5Y7rWYYh0zcM2G3VYmj+ToUu/psb/TC4fevKszWpjT8nXv7k6b6Ys8XbxBRglNB7jcLze1TM8zKG+h+kpiJb62jZjK5AcbAYOCnNfuoeAvRPwYsiXfwo6bPPZNsqrdKu+95fbTcqiu2Jnw5dP8aQEKzoAvkB48PJ9m7wE7cq81nRAbVzkVyBxHn5G9W1vT8yEmm2+gr8saJSKT4Gn3KR6gZV+DuMwMWAOvB5aqW3gDdGPqLu0rUz2BXEzVoIDuOodkVPtWjNyzdUicHFHiwILRtgbNO5G1uPThhpCyKLD4aTH9BKgry85yLza4FF+mOLAIw8wvIV4YbwOUv+nm5n+7RL0MO6gk17V+WmxGiCBmtNkukVSSuVuI1pb5d1ObsSWADeBR+FO3WkrvcVG9M6Na+c8Wgfnl0k6zzWEzmRSlkhtMqA== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199021)(46966006)(40470700004)(36840700001)(40460700003)(70206006)(70586007)(6636002)(4326008)(7696005)(316002)(110136005)(36756003)(478600001)(86362001)(83380400001)(47076005)(426003)(1076003)(26005)(186003)(336012)(36860700001)(4001150100001)(8676002)(5660300002)(2906002)(44832011)(30864003)(8936002)(6666004)(40480700001)(82310400005)(81166007)(41300700001)(82740400003)(2616005)(17423001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 09:39:22.0391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66f3ce57-9479-40b4-6669-08db52ccc42d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB7854 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Implement vmvnq using the new MVE builtins framework. 2022-12-12 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N_NO_F): New. (vmvnq): New. * config/arm/arm-mve-builtins-base.def (vmvnq): New. * config/arm/arm-mve-builtins-base.h (vmvnq): New. * config/arm/arm_mve.h (vmvnq): Remove. (vmvnq_m): Remove. (vmvnq_x): Remove. (vmvnq_s8): Remove. (vmvnq_s16): Remove. (vmvnq_s32): Remove. (vmvnq_n_s16): Remove. (vmvnq_n_s32): Remove. (vmvnq_u8): Remove. (vmvnq_u16): Remove. (vmvnq_u32): Remove. (vmvnq_n_u16): Remove. (vmvnq_n_u32): Remove. (vmvnq_m_u8): Remove. (vmvnq_m_s8): Remove. (vmvnq_m_u16): Remove. (vmvnq_m_s16): Remove. (vmvnq_m_u32): Remove. (vmvnq_m_s32): Remove. (vmvnq_m_n_s16): Remove. (vmvnq_m_n_u16): Remove. (vmvnq_m_n_s32): Remove. (vmvnq_m_n_u32): Remove. (vmvnq_x_s8): Remove. (vmvnq_x_s16): Remove. (vmvnq_x_s32): Remove. (vmvnq_x_u8): Remove. (vmvnq_x_u16): Remove. (vmvnq_x_u32): Remove. (vmvnq_x_n_s16): Remove. (vmvnq_x_n_s32): Remove. (vmvnq_x_n_u16): Remove. (vmvnq_x_n_u32): Remove. (__arm_vmvnq_s8): Remove. (__arm_vmvnq_s16): Remove. (__arm_vmvnq_s32): Remove. (__arm_vmvnq_n_s16): Remove. (__arm_vmvnq_n_s32): Remove. (__arm_vmvnq_u8): Remove. (__arm_vmvnq_u16): Remove. (__arm_vmvnq_u32): Remove. (__arm_vmvnq_n_u16): Remove. (__arm_vmvnq_n_u32): Remove. (__arm_vmvnq_m_u8): Remove. (__arm_vmvnq_m_s8): Remove. (__arm_vmvnq_m_u16): Remove. (__arm_vmvnq_m_s16): Remove. (__arm_vmvnq_m_u32): Remove. (__arm_vmvnq_m_s32): Remove. (__arm_vmvnq_m_n_s16): Remove. (__arm_vmvnq_m_n_u16): Remove. (__arm_vmvnq_m_n_s32): Remove. (__arm_vmvnq_m_n_u32): Remove. (__arm_vmvnq_x_s8): Remove. (__arm_vmvnq_x_s16): Remove. (__arm_vmvnq_x_s32): Remove. (__arm_vmvnq_x_u8): Remove. (__arm_vmvnq_x_u16): Remove. (__arm_vmvnq_x_u32): Remove. (__arm_vmvnq_x_n_s16): Remove. (__arm_vmvnq_x_n_s32): Remove. (__arm_vmvnq_x_n_u16): Remove. (__arm_vmvnq_x_n_u32): Remove. (__arm_vmvnq): Remove. (__arm_vmvnq_m): Remove. (__arm_vmvnq_x): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 10 + gcc/config/arm/arm-mve-builtins-base.def | 1 + gcc/config/arm/arm-mve-builtins-base.h | 1 + gcc/config/arm/arm_mve.h | 438 ----------------------- 4 files changed, 12 insertions(+), 438 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index 2fb81c197da..6286d4a147a 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -103,6 +103,15 @@ namespace arm_mve { UNSPEC##_M_S, UNSPEC##_M_U, UNSPEC##_M_F, \ -1, -1, -1)) + /* Helper for builtins with RTX codes, _m predicated and _n + overrides, but no floating-point version. */ +#define FUNCTION_WITH_RTX_M_N_NO_F(NAME, RTX, UNSPEC) FUNCTION \ + (NAME, unspec_based_mve_function_exact_insn, \ + (RTX, RTX, UNKNOWN, \ + UNSPEC##_N_S, UNSPEC##_N_U, -1, \ + UNSPEC##_M_S, UNSPEC##_M_U, -1, \ + UNSPEC##_M_N_S, UNSPEC##_M_N_U, -1)) + /* Helper for builtins with RTX codes, _m predicated and _n overrides. */ #define FUNCTION_WITH_RTX_M_N_NO_N_F(NAME, RTX, UNSPEC) FUNCTION \ (NAME, unspec_based_mve_function_exact_insn, \ @@ -306,6 +315,7 @@ FUNCTION_WITHOUT_N_NO_F (vmovnbq, VMOVNBQ) FUNCTION_WITHOUT_N_NO_F (vmovntq, VMOVNTQ) FUNCTION_WITHOUT_N_NO_F (vmulhq, VMULHQ) FUNCTION_WITH_RTX_M_N (vmulq, MULT, VMULQ) +FUNCTION_WITH_RTX_M_N_NO_F (vmvnq, NOT, VMVNQ) FUNCTION (vnegq, unspec_based_mve_function_exact_insn, (NEG, NEG, NEG, -1, -1, -1, VNEGQ_M_S, -1, VNEGQ_M_F, -1, -1, -1)) FUNCTION_WITH_RTX_M_N_NO_N_F (vorrq, IOR, VORRQ) FUNCTION_WITHOUT_N_NO_U_F (vqabsq, VQABSQ) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index e53cb2c1992..141d057924e 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -75,6 +75,7 @@ DEF_MVE_FUNCTION (vmovnbq, binary_move_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vmovntq, binary_move_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vmulhq, binary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vmulq, binary_opt_n, all_integer, mx_or_none) +DEF_MVE_FUNCTION (vmvnq, mvn, all_integer, mx_or_none) DEF_MVE_FUNCTION (vnegq, unary, all_signed, mx_or_none) DEF_MVE_FUNCTION (vorrq, binary_orrq, all_integer, mx_or_none) DEF_MVE_FUNCTION (vqabsq, unary, all_signed, m_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 49c60536961..b1783a2c917 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -88,6 +88,7 @@ extern const function_base *const vmovnbq; extern const function_base *const vmovntq; extern const function_base *const vmulhq; extern const function_base *const vmulq; +extern const function_base *const vmvnq; extern const function_base *const vnegq; extern const function_base *const vorrq; extern const function_base *const vqabsq; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 76c45a28eb3..69ded8703cd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -42,7 +42,6 @@ #ifndef __ARM_MVE_PRESERVE_USER_NAMESPACE #define vst4q(__addr, __value) __arm_vst4q(__addr, __value) -#define vmvnq(__a) __arm_vmvnq(__a) #define vornq(__a, __b) __arm_vornq(__a, __b) #define vmulltq_int(__a, __b) __arm_vmulltq_int(__a, __b) #define vmullbq_int(__a, __b) __arm_vmullbq_int(__a, __b) @@ -56,7 +55,6 @@ #define vbicq_m_n(__a, __imm, __p) __arm_vbicq_m_n(__a, __imm, __p) #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) #define vpselq(__a, __b, __p) __arm_vpselq(__a, __b, __p) -#define vmvnq_m(__inactive, __a, __p) __arm_vmvnq_m(__inactive, __a, __p) #define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm) #define vsliq(__a, __b, __imm) __arm_vsliq(__a, __b, __imm) #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) @@ -153,7 +151,6 @@ #define vhcaddq_rot90_x(__a, __b, __p) __arm_vhcaddq_rot90_x(__a, __b, __p) #define vhcaddq_rot270_x(__a, __b, __p) __arm_vhcaddq_rot270_x(__a, __b, __p) #define vbicq_x(__a, __b, __p) __arm_vbicq_x(__a, __b, __p) -#define vmvnq_x(__a, __p) __arm_vmvnq_x(__a, __p) #define vornq_x(__a, __b, __p) __arm_vornq_x(__a, __b, __p) #define vadciq(__a, __b, __carry_out) __arm_vadciq(__a, __b, __carry_out) #define vadciq_m(__inactive, __a, __b, __carry_out, __p) __arm_vadciq_m(__inactive, __a, __b, __carry_out, __p) @@ -227,11 +224,6 @@ #define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) -#define vmvnq_s8(__a) __arm_vmvnq_s8(__a) -#define vmvnq_s16(__a) __arm_vmvnq_s16(__a) -#define vmvnq_s32(__a) __arm_vmvnq_s32(__a) -#define vmvnq_n_s16( __imm) __arm_vmvnq_n_s16( __imm) -#define vmvnq_n_s32( __imm) __arm_vmvnq_n_s32( __imm) #define vcvtaq_s16_f16(__a) __arm_vcvtaq_s16_f16(__a) #define vcvtaq_s32_f32(__a) __arm_vcvtaq_s32_f32(__a) #define vcvtnq_s16_f16(__a) __arm_vcvtnq_s16_f16(__a) @@ -242,11 +234,6 @@ #define vcvtmq_s32_f32(__a) __arm_vcvtmq_s32_f32(__a) #define vcvtq_s16_f16(__a) __arm_vcvtq_s16_f16(__a) #define vcvtq_s32_f32(__a) __arm_vcvtq_s32_f32(__a) -#define vmvnq_u8(__a) __arm_vmvnq_u8(__a) -#define vmvnq_u16(__a) __arm_vmvnq_u16(__a) -#define vmvnq_u32(__a) __arm_vmvnq_u32(__a) -#define vmvnq_n_u16( __imm) __arm_vmvnq_n_u16( __imm) -#define vmvnq_n_u32( __imm) __arm_vmvnq_n_u32( __imm) #define vcvtq_u16_f16(__a) __arm_vcvtq_u16_f16(__a) #define vcvtq_u32_f32(__a) __arm_vcvtq_u32_f32(__a) #define vcvtpq_u16_f16(__a) __arm_vcvtpq_u16_f16(__a) @@ -362,26 +349,20 @@ #define vshlcq_u32(__a, __b, __imm) __arm_vshlcq_u32(__a, __b, __imm) #define vpselq_u8(__a, __b, __p) __arm_vpselq_u8(__a, __b, __p) #define vpselq_s8(__a, __b, __p) __arm_vpselq_s8(__a, __b, __p) -#define vmvnq_m_u8(__inactive, __a, __p) __arm_vmvnq_m_u8(__inactive, __a, __p) #define vsriq_n_u8(__a, __b, __imm) __arm_vsriq_n_u8(__a, __b, __imm) #define vsliq_n_u8(__a, __b, __imm) __arm_vsliq_n_u8(__a, __b, __imm) -#define vmvnq_m_s8(__inactive, __a, __p) __arm_vmvnq_m_s8(__inactive, __a, __p) #define vsriq_n_s8(__a, __b, __imm) __arm_vsriq_n_s8(__a, __b, __imm) #define vsliq_n_s8(__a, __b, __imm) __arm_vsliq_n_s8(__a, __b, __imm) #define vpselq_u16(__a, __b, __p) __arm_vpselq_u16(__a, __b, __p) #define vpselq_s16(__a, __b, __p) __arm_vpselq_s16(__a, __b, __p) -#define vmvnq_m_u16(__inactive, __a, __p) __arm_vmvnq_m_u16(__inactive, __a, __p) #define vsriq_n_u16(__a, __b, __imm) __arm_vsriq_n_u16(__a, __b, __imm) #define vsliq_n_u16(__a, __b, __imm) __arm_vsliq_n_u16(__a, __b, __imm) -#define vmvnq_m_s16(__inactive, __a, __p) __arm_vmvnq_m_s16(__inactive, __a, __p) #define vsriq_n_s16(__a, __b, __imm) __arm_vsriq_n_s16(__a, __b, __imm) #define vsliq_n_s16(__a, __b, __imm) __arm_vsliq_n_s16(__a, __b, __imm) #define vpselq_u32(__a, __b, __p) __arm_vpselq_u32(__a, __b, __p) #define vpselq_s32(__a, __b, __p) __arm_vpselq_s32(__a, __b, __p) -#define vmvnq_m_u32(__inactive, __a, __p) __arm_vmvnq_m_u32(__inactive, __a, __p) #define vsriq_n_u32(__a, __b, __imm) __arm_vsriq_n_u32(__a, __b, __imm) #define vsliq_n_u32(__a, __b, __imm) __arm_vsliq_n_u32(__a, __b, __imm) -#define vmvnq_m_s32(__inactive, __a, __p) __arm_vmvnq_m_s32(__inactive, __a, __p) #define vsriq_n_s32(__a, __b, __imm) __arm_vsriq_n_s32(__a, __b, __imm) #define vsliq_n_s32(__a, __b, __imm) __arm_vsliq_n_s32(__a, __b, __imm) #define vpselq_u64(__a, __b, __p) __arm_vpselq_u64(__a, __b, __p) @@ -390,7 +371,6 @@ #define vcvtbq_m_f32_f16(__inactive, __a, __p) __arm_vcvtbq_m_f32_f16(__inactive, __a, __p) #define vcvttq_m_f16_f32(__a, __b, __p) __arm_vcvttq_m_f16_f32(__a, __b, __p) #define vcvttq_m_f32_f16(__inactive, __a, __p) __arm_vcvttq_m_f32_f16(__inactive, __a, __p) -#define vmvnq_m_n_s16(__inactive, __imm, __p) __arm_vmvnq_m_n_s16(__inactive, __imm, __p) #define vcmlaq_f16(__a, __b, __c) __arm_vcmlaq_f16(__a, __b, __c) #define vcmlaq_rot180_f16(__a, __b, __c) __arm_vcmlaq_rot180_f16(__a, __b, __c) #define vcmlaq_rot270_f16(__a, __b, __c) __arm_vcmlaq_rot270_f16(__a, __b, __c) @@ -404,12 +384,10 @@ #define vcvtpq_m_s16_f16(__inactive, __a, __p) __arm_vcvtpq_m_s16_f16(__inactive, __a, __p) #define vcvtq_m_s16_f16(__inactive, __a, __p) __arm_vcvtq_m_s16_f16(__inactive, __a, __p) #define vpselq_f16(__a, __b, __p) __arm_vpselq_f16(__a, __b, __p) -#define vmvnq_m_n_u16(__inactive, __imm, __p) __arm_vmvnq_m_n_u16(__inactive, __imm, __p) #define vcvtmq_m_u16_f16(__inactive, __a, __p) __arm_vcvtmq_m_u16_f16(__inactive, __a, __p) #define vcvtnq_m_u16_f16(__inactive, __a, __p) __arm_vcvtnq_m_u16_f16(__inactive, __a, __p) #define vcvtpq_m_u16_f16(__inactive, __a, __p) __arm_vcvtpq_m_u16_f16(__inactive, __a, __p) #define vcvtq_m_u16_f16(__inactive, __a, __p) __arm_vcvtq_m_u16_f16(__inactive, __a, __p) -#define vmvnq_m_n_s32(__inactive, __imm, __p) __arm_vmvnq_m_n_s32(__inactive, __imm, __p) #define vcmlaq_f32(__a, __b, __c) __arm_vcmlaq_f32(__a, __b, __c) #define vcmlaq_rot180_f32(__a, __b, __c) __arm_vcmlaq_rot180_f32(__a, __b, __c) #define vcmlaq_rot270_f32(__a, __b, __c) __arm_vcmlaq_rot270_f32(__a, __b, __c) @@ -423,7 +401,6 @@ #define vcvtpq_m_s32_f32(__inactive, __a, __p) __arm_vcvtpq_m_s32_f32(__inactive, __a, __p) #define vcvtq_m_s32_f32(__inactive, __a, __p) __arm_vcvtq_m_s32_f32(__inactive, __a, __p) #define vpselq_f32(__a, __b, __p) __arm_vpselq_f32(__a, __b, __p) -#define vmvnq_m_n_u32(__inactive, __imm, __p) __arm_vmvnq_m_n_u32(__inactive, __imm, __p) #define vcvtmq_m_u32_f32(__inactive, __a, __p) __arm_vcvtmq_m_u32_f32(__inactive, __a, __p) #define vcvtnq_m_u32_f32(__inactive, __a, __p) __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) #define vcvtpq_m_u32_f32(__inactive, __a, __p) __arm_vcvtpq_m_u32_f32(__inactive, __a, __p) @@ -864,16 +841,6 @@ #define vbicq_x_u8(__a, __b, __p) __arm_vbicq_x_u8(__a, __b, __p) #define vbicq_x_u16(__a, __b, __p) __arm_vbicq_x_u16(__a, __b, __p) #define vbicq_x_u32(__a, __b, __p) __arm_vbicq_x_u32(__a, __b, __p) -#define vmvnq_x_s8(__a, __p) __arm_vmvnq_x_s8(__a, __p) -#define vmvnq_x_s16(__a, __p) __arm_vmvnq_x_s16(__a, __p) -#define vmvnq_x_s32(__a, __p) __arm_vmvnq_x_s32(__a, __p) -#define vmvnq_x_u8(__a, __p) __arm_vmvnq_x_u8(__a, __p) -#define vmvnq_x_u16(__a, __p) __arm_vmvnq_x_u16(__a, __p) -#define vmvnq_x_u32(__a, __p) __arm_vmvnq_x_u32(__a, __p) -#define vmvnq_x_n_s16( __imm, __p) __arm_vmvnq_x_n_s16( __imm, __p) -#define vmvnq_x_n_s32( __imm, __p) __arm_vmvnq_x_n_s32( __imm, __p) -#define vmvnq_x_n_u16( __imm, __p) __arm_vmvnq_x_n_u16( __imm, __p) -#define vmvnq_x_n_u32( __imm, __p) __arm_vmvnq_x_n_u32( __imm, __p) #define vornq_x_s8(__a, __b, __p) __arm_vornq_x_s8(__a, __b, __p) #define vornq_x_s16(__a, __b, __p) __arm_vornq_x_s16(__a, __b, __p) #define vornq_x_s32(__a, __b, __p) __arm_vornq_x_s32(__a, __b, __p) @@ -1096,76 +1063,6 @@ __arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_s8 (int8x16_t __a) -{ - return __builtin_mve_vmvnq_sv16qi (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_s16 (int16x8_t __a) -{ - return __builtin_mve_vmvnq_sv8hi (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_s32 (int32x4_t __a) -{ - return __builtin_mve_vmvnq_sv4si (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_n_s16 (const int16_t __imm) -{ - return __builtin_mve_vmvnq_n_sv8hi (__imm); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_n_s32 (const int32_t __imm) -{ - return __builtin_mve_vmvnq_n_sv4si (__imm); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_u8 (uint8x16_t __a) -{ - return __builtin_mve_vmvnq_uv16qi (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_u16 (uint16x8_t __a) -{ - return __builtin_mve_vmvnq_uv8hi (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_u32 (uint32x4_t __a) -{ - return __builtin_mve_vmvnq_uv4si (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_n_u16 (const int __imm) -{ - return __builtin_mve_vmvnq_n_uv8hi (__imm); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_n_u32 (const int __imm) -{ - return __builtin_mve_vmvnq_n_uv4si (__imm); -} - __extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vctp16q (uint32_t __a) @@ -1681,13 +1578,6 @@ __arm_vpselq_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv16qi (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv16qi (__inactive, __a, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) @@ -1702,13 +1592,6 @@ __arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv16qi (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) @@ -1737,13 +1620,6 @@ __arm_vpselq_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv8hi (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) @@ -1758,13 +1634,6 @@ __arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv8hi (__inactive, __a, __p); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) @@ -1793,13 +1662,6 @@ __arm_vpselq_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv4si (__a, __b, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv4si (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) @@ -1814,13 +1676,6 @@ __arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv4si (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) @@ -1849,34 +1704,6 @@ __arm_vpselq_s64 (int64x2_t __a, int64x2_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv2di (__a, __b, __p); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_n_s16 (int16x8_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_sv8hi (__inactive, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_n_u16 (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_uv8hi (__inactive, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_n_s32 (int32x4_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_sv4si (__inactive, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m_n_u32 (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_uv4si (__inactive, __imm, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -4474,76 +4301,6 @@ __arm_vbicq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) return __builtin_mve_vbicq_m_uv4si (__arm_vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_s8 (int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv16qi (__arm_vuninitializedq_s8 (), __a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_s16 (int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv8hi (__arm_vuninitializedq_s16 (), __a, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_s32 (int32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_sv4si (__arm_vuninitializedq_s32 (), __a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_u8 (uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv16qi (__arm_vuninitializedq_u8 (), __a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_u16 (uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv8hi (__arm_vuninitializedq_u16 (), __a, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_u32 (uint32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_uv4si (__arm_vuninitializedq_u32 (), __a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_n_s16 (const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_sv8hi (__arm_vuninitializedq_s16 (), __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_n_s32 (const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_sv4si (__arm_vuninitializedq_s32 (), __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_n_u16 (const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_uv8hi (__arm_vuninitializedq_u16 (), __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x_n_u32 (const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vmvnq_m_n_uv4si (__arm_vuninitializedq_u32 (), __imm, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) @@ -7041,48 +6798,6 @@ __arm_vst4q (uint32_t * __addr, uint32x4x4_t __value) __arm_vst4q_u32 (__addr, __value); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (int8x16_t __a) -{ - return __arm_vmvnq_s8 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (int16x8_t __a) -{ - return __arm_vmvnq_s16 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (int32x4_t __a) -{ - return __arm_vmvnq_s32 (__a); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (uint8x16_t __a) -{ - return __arm_vmvnq_u8 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (uint16x8_t __a) -{ - return __arm_vmvnq_u16 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq (uint32x4_t __a) -{ - return __arm_vmvnq_u32 (__a); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq (uint8x16_t __a, uint8x16_t __b) @@ -7517,13 +7232,6 @@ __arm_vpselq (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) return __arm_vpselq_s8 (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_u8 (__inactive, __a, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (uint8x16_t __a, uint8x16_t __b, const int __imm) @@ -7538,13 +7246,6 @@ __arm_vsliq (uint8x16_t __a, uint8x16_t __b, const int __imm) return __arm_vsliq_n_u8 (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_s8 (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int8x16_t __a, int8x16_t __b, const int __imm) @@ -7573,13 +7274,6 @@ __arm_vpselq (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) return __arm_vpselq_s16 (__a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_u16 (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (uint16x8_t __a, uint16x8_t __b, const int __imm) @@ -7594,13 +7288,6 @@ __arm_vsliq (uint16x8_t __a, uint16x8_t __b, const int __imm) return __arm_vsliq_n_u16 (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_s16 (__inactive, __a, __p); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int16x8_t __a, int16x8_t __b, const int __imm) @@ -7629,13 +7316,6 @@ __arm_vpselq (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) return __arm_vpselq_s32 (__a, __b, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_u32 (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (uint32x4_t __a, uint32x4_t __b, const int __imm) @@ -7650,13 +7330,6 @@ __arm_vsliq (uint32x4_t __a, uint32x4_t __b, const int __imm) return __arm_vsliq_n_u32 (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_m_s32 (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq (int32x4_t __a, int32x4_t __b, const int __imm) @@ -7685,34 +7358,6 @@ __arm_vpselq (int64x2_t __a, int64x2_t __b, mve_pred16_t __p) return __arm_vpselq_s64 (__a, __b, __p); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (int16x8_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __arm_vmvnq_m_n_s16 (__inactive, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __arm_vmvnq_m_n_u16 (__inactive, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (int32x4_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __arm_vmvnq_m_n_s32 (__inactive, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_m (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) -{ - return __arm_vmvnq_m_n_u32 (__inactive, __imm, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -9883,48 +9528,6 @@ __arm_vbicq_x (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) return __arm_vbicq_x_u32 (__a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_s8 (__a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_s16 (__a, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (int32x4_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_s32 (__a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_u8 (__a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_u16 (__a, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmvnq_x (uint32x4_t __a, mve_pred16_t __p) -{ - return __arm_vmvnq_x_u32 (__a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vornq_x (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) @@ -11988,15 +11591,6 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) -#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) - #define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ @@ -12879,15 +12473,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) -#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) - #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -13431,15 +13016,6 @@ extern void *__ARM_undef; -#define __arm_vmvnq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ @@ -13617,20 +13193,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) -#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) - #define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \