From patchwork Wed May 10 13:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 69068 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 01CDC3856248 for ; Wed, 10 May 2023 13:38:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 01CDC3856248 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683725937; bh=R912pHK/BJSGJXSyaLvUqa2kkmLv7YmZ9CE8imJ9k70=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=O4KtmUmSsvm3qznLyEFy0S8xd+VawHTK07tOYsfM7AoD0XuwR/kUIegQRL6A4lqbT 0BAOh9OGRvMOM430cJwl1zmG5neueaDmFTtpt3EYD7QnoeoTsRxQZxqyRJuv1bj72o /0Yr0xq5D0m3+zdkEBOzI7FYA2egWbdkwqLe8Gyo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2074.outbound.protection.outlook.com [40.107.22.74]) by sourceware.org (Postfix) with ESMTPS id 0F4663852771 for ; Wed, 10 May 2023 13:31:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0F4663852771 Received: from AS8P189CA0009.EURP189.PROD.OUTLOOK.COM (2603:10a6:20b:31f::19) by DB3PR08MB8820.eurprd08.prod.outlook.com (2603:10a6:10:438::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.33; Wed, 10 May 2023 13:31:08 +0000 Received: from AM7EUR03FT027.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:31f:cafe::e9) by AS8P189CA0009.outlook.office365.com (2603:10a6:20b:31f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.19 via Frontend Transport; Wed, 10 May 2023 13:31:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT027.mail.protection.outlook.com (100.127.140.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.20 via Frontend Transport; Wed, 10 May 2023 13:31:07 +0000 Received: ("Tessian outbound 3570909035da:v136"); Wed, 10 May 2023 13:31:07 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 3cd6a3e214992c98 X-CR-MTA-TID: 64aa7808 Received: from e2c3ea589ace.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id CF040C42-7930-4D4F-812A-15183AB10538.1; Wed, 10 May 2023 13:30:56 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id e2c3ea589ace.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 10 May 2023 13:30:56 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qv+ZyesmJLENNH+N406k3z82djW54N6iAd2obW5hE6AwV2x1sNC5njxdNUW+4LCegnKWhKaS35yGIqmA+/C1J0S3TprWEeqvfwMqYdZy/v1bQmFp4Xzn3VFRsFnMJC6MPdiwyMwgo2uv6E2vDib8ZoVK4QqAK/H1xQSFN9jcwSRUrPf5sfAACyMBJ+FEj8+omot53tGdhWldMcx4uyN9x1s5tvPadGuczUdobwAlhJhReiVmkkOtW0mpUnTJDQd3yxv7rhbTk+VXp4iAcrk6XexO+ZVdtW9N7QUFkkV4Wxxp5ZtjLYAmDlrpeVwtXmoURurtmeeyNb/4MKheFDGLKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=R912pHK/BJSGJXSyaLvUqa2kkmLv7YmZ9CE8imJ9k70=; b=l3esP1eIXtDHLXIqawjx6uYI7PmeGIVS3t0w8pmKMnotcOCDy44eqxf/2hpg/uxTg0HsQWk2+PJWBU1WV23RQ8Y1cBmgFba7hn4YGWZZY8CA5wrro3Em+LxkWY/XxbIEHCBTay9H/5Bx75y9jxUW4j4/Qp1kOp1b3drAUvCNu6PeyZj+Np6pRBGxfjthUNR4SwgI3u4bXtaEv/Fs+O6x5Sc2R1Zaz296KfVxahOJmzEQTqs+ahafT0b+Bb283ZtW4S/nXXRIaYV8K4OEqcPR8N1j4/Ek/sPACzsKlkilNgfGoDH+HBim14siqYDghVS2u31OZxgAHEoHk6fl9bWrSQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from DB6P195CA0014.EURP195.PROD.OUTLOOK.COM (2603:10a6:4:cb::24) by PAVPR08MB9604.eurprd08.prod.outlook.com (2603:10a6:102:31b::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.33; Wed, 10 May 2023 13:30:45 +0000 Received: from DBAEUR03FT038.eop-EUR03.prod.protection.outlook.com (2603:10a6:4:cb:cafe::bc) by DB6P195CA0014.outlook.office365.com (2603:10a6:4:cb::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.32 via Frontend Transport; Wed, 10 May 2023 13:30:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT038.mail.protection.outlook.com (100.127.143.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.19 via Frontend Transport; Wed, 10 May 2023 13:30:45 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 10 May 2023 13:30:42 +0000 Received: from e129018.arm.com (10.57.23.51) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Wed, 10 May 2023 13:30:42 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 05/20] arm: [MVE intrinsics] rework vrev16q vrev32q vrev64q Date: Wed, 10 May 2023 15:30:21 +0200 Message-ID: <20230510133036.596530-5-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230510133036.596530-1-christophe.lyon@arm.com> References: <20230510133036.596530-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT038:EE_|PAVPR08MB9604:EE_|AM7EUR03FT027:EE_|DB3PR08MB8820:EE_ X-MS-Office365-Filtering-Correlation-Id: a05daee6-530d-47bd-2267-08db515acfe1 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: yxPU36ddXVw4gO5fNiF9+U1wJx3rgSKdjcNW+sn2V4/waKH2Fve6UOeonmPgLMdOTLGDBTFog190ycxDflRxZFotU2GA0A+elwyXW8Jd1fTLTFX1cgmENHec4DnLTr1I+QlqwAidIflekZnEF+uJZuR+V5MT8Wn7oTB61WrPa2YuXuywOEe50wctAp9CgfBXz78K0YaOvoP5+ypBUC1/fcy86W4WBUpOLnrpxRb0QSfMtU7PjLmbe+Bl3qMvFCPupADE64rlnuco+jDMtMHpXTboiklJRRHyrTKP0PlolnFMeXITKyTxw8hDE4OxR8KaCQ9xda2WA7Q2jzSFDmTdo6S5AV6wS7OuBcB8gjlK4VQ1ItdYKKjwh6t143al0VIroFTrVghXBoRtP9iEzyDZNyhY7QA+EAfWMagOuNalVsvHJTlzt6iF/HhPqvYxGz3aJcCxsEGjBr9s8Yl6N8ZMNBdsIaZxOHAjnETxdE+vqu+T55eI5RFE6B+2Yst1ydpX1p7RSmiD/ba7Rq6ya8OGuxMLw84E67n+l2AEqSiZgvl3Pw7SipmzwhI+1awGicNx3rmXNZ4IMdAI0ZjvtrBs2dZKBAEhmcUUi+Uy431kwj49MZ80wD2+jWyU3tTBcbN1ddkOPFaWrOQ89+46gEucVlyzUxyVLLuOoxh3GO3O1f7T9oOKg9eXkHF0gK/9Vl2O+s1ljwcrHLKEdxob8L90me+c32WP7a4v/oxWen0hfyQ= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(396003)(346002)(136003)(376002)(451199021)(40470700004)(46966006)(36840700001)(36860700001)(6666004)(40460700003)(82740400003)(41300700001)(82310400005)(36756003)(356005)(4001150100001)(40480700001)(86362001)(44832011)(2906002)(5660300002)(8676002)(81166007)(8936002)(30864003)(70206006)(70586007)(6636002)(426003)(478600001)(4326008)(316002)(83380400001)(7696005)(336012)(47076005)(1076003)(26005)(110136005)(186003)(2616005)(36900700001)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9604 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT027.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 7b1fd79d-433b-4fbc-c552-08db515ac248 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: toXCSG90g7Gcqn665N8XkFvIRqvJKlfPhiwuSLzlTV/U2pTMLkQcRCEi8W94JtwRTGw/gWYpgGw7v97/ZwJe0fKxzKEiA0Kk1H5LyKl7uDRbMLy0s5yI2jLpwBF9AHzHW2b82GtmyQjQ4pxlJobonyCNcPnRy3vSEvPo6m9QPX1bY7gWxe2w3sdD6AIjc9vkFbRs+E+10bkXAGOHSjUG2TNFj7vHtPWZ421UwXXh6O/2UGVJpZhMRpBhVFg8IQqqkScAUWWA0TiVc/qG7qtrzWgeXWYIGcP7woAGdxaAohYu/g1WZHKaFHNWJvJI91QOhWlagN0b9VEpg4mDxaatwy/APVjyj11NzbWuNFiu7LulCr3leGTVpZAtWmwokVXflJiRFaU6H/r3Ry9DPg7insWOCpnb+BW3WdQLiOP/GRcRikn+p/ObKnBshU0J2+0ZUVoXEUNZN4UbUghu26aZIx1gOcmCqF/DFK0yZGEwmDE46BknNOrNBiJpxj2SbzWNSC9EK1Kb5byTHm2ThoS6MZz7iU0cKLiIpmbwjapUKR/FAmDB7zTvF9b9XjRTHsQN853thT8xjLqkj2LTmYG/G69VNLTxFRBdGuVZ2EUwZ5pr5yb+Se8zMlOKttY5cAcV4DAn9nH9+td7t248k3+mhaBNCHB5+JZgEaLoyZstBs5PhbIvGnhbMMLM0Aui8ycWTm2AnUEhmRbuqSqsmBLNwA== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199021)(40470700004)(46966006)(36840700001)(478600001)(86362001)(2616005)(47076005)(83380400001)(36860700001)(336012)(426003)(6666004)(40480700001)(1076003)(26005)(7696005)(81166007)(316002)(110136005)(4326008)(70206006)(70586007)(82740400003)(6636002)(186003)(41300700001)(40460700003)(8676002)(8936002)(5660300002)(44832011)(4001150100001)(2906002)(30864003)(82310400005)(36756003)(579004)(559001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 13:31:07.8664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a05daee6-530d-47bd-2267-08db515acfe1 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT027.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB8820 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Implement vrev16q, vrev32q, vrev64q using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q): New. * config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm_mve.h (vrev16q): Remove. (vrev32q): Remove. (vrev64q): Remove. (vrev64q_m): Remove. (vrev16q_m): Remove. (vrev32q_m): Remove. (vrev16q_x): Remove. (vrev32q_x): Remove. (vrev64q_x): Remove. (vrev64q_f16): Remove. (vrev64q_f32): Remove. (vrev32q_f16): Remove. (vrev16q_s8): Remove. (vrev32q_s8): Remove. (vrev32q_s16): Remove. (vrev64q_s8): Remove. (vrev64q_s16): Remove. (vrev64q_s32): Remove. (vrev64q_u8): Remove. (vrev64q_u16): Remove. (vrev64q_u32): Remove. (vrev32q_u8): Remove. (vrev32q_u16): Remove. (vrev16q_u8): Remove. (vrev64q_m_u8): Remove. (vrev64q_m_s8): Remove. (vrev64q_m_u16): Remove. (vrev64q_m_s16): Remove. (vrev64q_m_u32): Remove. (vrev64q_m_s32): Remove. (vrev16q_m_s8): Remove. (vrev32q_m_f16): Remove. (vrev16q_m_u8): Remove. (vrev32q_m_s8): Remove. (vrev64q_m_f16): Remove. (vrev32q_m_u8): Remove. (vrev32q_m_s16): Remove. (vrev64q_m_f32): Remove. (vrev32q_m_u16): Remove. (vrev16q_x_s8): Remove. (vrev16q_x_u8): Remove. (vrev32q_x_s8): Remove. (vrev32q_x_s16): Remove. (vrev32q_x_u8): Remove. (vrev32q_x_u16): Remove. (vrev64q_x_s8): Remove. (vrev64q_x_s16): Remove. (vrev64q_x_s32): Remove. (vrev64q_x_u8): Remove. (vrev64q_x_u16): Remove. (vrev64q_x_u32): Remove. (vrev32q_x_f16): Remove. (vrev64q_x_f16): Remove. (vrev64q_x_f32): Remove. (__arm_vrev16q_s8): Remove. (__arm_vrev32q_s8): Remove. (__arm_vrev32q_s16): Remove. (__arm_vrev64q_s8): Remove. (__arm_vrev64q_s16): Remove. (__arm_vrev64q_s32): Remove. (__arm_vrev64q_u8): Remove. (__arm_vrev64q_u16): Remove. (__arm_vrev64q_u32): Remove. (__arm_vrev32q_u8): Remove. (__arm_vrev32q_u16): Remove. (__arm_vrev16q_u8): Remove. (__arm_vrev64q_m_u8): Remove. (__arm_vrev64q_m_s8): Remove. (__arm_vrev64q_m_u16): Remove. (__arm_vrev64q_m_s16): Remove. (__arm_vrev64q_m_u32): Remove. (__arm_vrev64q_m_s32): Remove. (__arm_vrev16q_m_s8): Remove. (__arm_vrev16q_m_u8): Remove. (__arm_vrev32q_m_s8): Remove. (__arm_vrev32q_m_u8): Remove. (__arm_vrev32q_m_s16): Remove. (__arm_vrev32q_m_u16): Remove. (__arm_vrev16q_x_s8): Remove. (__arm_vrev16q_x_u8): Remove. (__arm_vrev32q_x_s8): Remove. (__arm_vrev32q_x_s16): Remove. (__arm_vrev32q_x_u8): Remove. (__arm_vrev32q_x_u16): Remove. (__arm_vrev64q_x_s8): Remove. (__arm_vrev64q_x_s16): Remove. (__arm_vrev64q_x_s32): Remove. (__arm_vrev64q_x_u8): Remove. (__arm_vrev64q_x_u16): Remove. (__arm_vrev64q_x_u32): Remove. (__arm_vrev64q_f16): Remove. (__arm_vrev64q_f32): Remove. (__arm_vrev32q_f16): Remove. (__arm_vrev32q_m_f16): Remove. (__arm_vrev64q_m_f16): Remove. (__arm_vrev64q_m_f32): Remove. (__arm_vrev32q_x_f16): Remove. (__arm_vrev64q_x_f16): Remove. (__arm_vrev64q_x_f32): Remove. (__arm_vrev16q): Remove. (__arm_vrev32q): Remove. (__arm_vrev64q): Remove. (__arm_vrev64q_m): Remove. (__arm_vrev16q_m): Remove. (__arm_vrev32q_m): Remove. (__arm_vrev16q_x): Remove. (__arm_vrev32q_x): Remove. (__arm_vrev64q_x): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 3 + gcc/config/arm/arm-mve-builtins-base.def | 5 + gcc/config/arm/arm-mve-builtins-base.h | 3 + gcc/config/arm/arm_mve.h | 820 ----------------------- 4 files changed, 11 insertions(+), 820 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index 14870f5b1aa..76294ddb7fb 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -293,6 +293,9 @@ FUNCTION_ONLY_N_NO_U_F (vqshrunbq, VQSHRUNBQ) FUNCTION_ONLY_N_NO_U_F (vqshruntq, VQSHRUNTQ) FUNCTION_WITH_M_N_NO_F (vqsubq, VQSUBQ) FUNCTION (vreinterpretq, vreinterpretq_impl,) +FUNCTION_WITHOUT_N_NO_F (vrev16q, VREV16Q) +FUNCTION_WITHOUT_N (vrev32q, VREV32Q) +FUNCTION_WITHOUT_N (vrev64q, VREV64Q) FUNCTION_WITHOUT_N_NO_F (vrhaddq, VRHADDQ) FUNCTION_WITHOUT_N_NO_F (vrmulhq, VRMULHQ) FUNCTION_ONLY_F (vrndq, VRNDQ) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index f05cecd9160..2602cbf20e3 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -72,6 +72,9 @@ DEF_MVE_FUNCTION (vqshrunbq, binary_rshift_narrow_unsigned, signed_16_32, m_or_n DEF_MVE_FUNCTION (vqshruntq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) DEF_MVE_FUNCTION (vqsubq, binary_opt_n, all_integer, m_or_none) DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_integer, none) +DEF_MVE_FUNCTION (vrev16q, unary, integer_8, mx_or_none) +DEF_MVE_FUNCTION (vrev32q, unary, integer_8_16, mx_or_none) +DEF_MVE_FUNCTION (vrev64q, unary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vrhaddq, binary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vrmulhq, binary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vrshlq, binary_round_lshift, all_integer, mx_or_none) @@ -114,6 +117,8 @@ DEF_MVE_FUNCTION (vmulq, binary_opt_n, all_float, mx_or_none) DEF_MVE_FUNCTION (vnegq, unary, all_float, mx_or_none) DEF_MVE_FUNCTION (vorrq, binary_orrq, all_float, mx_or_none) DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_float, none) +DEF_MVE_FUNCTION (vrev32q, unary, float16, mx_or_none) +DEF_MVE_FUNCTION (vrev64q, unary, all_float, mx_or_none) DEF_MVE_FUNCTION (vrndaq, unary, all_float, mx_or_none) DEF_MVE_FUNCTION (vrndmq, unary, all_float, mx_or_none) DEF_MVE_FUNCTION (vrndnq, unary, all_float, mx_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 179e1295fb2..eaea466712a 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -84,6 +84,9 @@ extern const function_base *const vqshrunbq; extern const function_base *const vqshruntq; extern const function_base *const vqsubq; extern const function_base *const vreinterpretq; +extern const function_base *const vrev16q; +extern const function_base *const vrev32q; +extern const function_base *const vrev64q; extern const function_base *const vrhaddq; extern const function_base *const vrmulhq; extern const function_base *const vrndaq; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 3eb8195060b..3692f600b37 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -48,9 +48,6 @@ #define vmovlbq(__a) __arm_vmovlbq(__a) #define vmovltq(__a) __arm_vmovltq(__a) #define vmvnq(__a) __arm_vmvnq(__a) -#define vrev16q(__a) __arm_vrev16q(__a) -#define vrev32q(__a) __arm_vrev32q(__a) -#define vrev64q(__a) __arm_vrev64q(__a) #define vaddlvq_p(__a, __p) __arm_vaddlvq_p(__a, __p) #define vornq(__a, __b) __arm_vornq(__a, __b) #define vmulltq_int(__a, __b) __arm_vmulltq_int(__a, __b) @@ -86,7 +83,6 @@ #define vrmlaldavhaq(__a, __b, __c) __arm_vrmlaldavhaq(__a, __b, __c) #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) #define vpselq(__a, __b, __p) __arm_vpselq(__a, __b, __p) -#define vrev64q_m(__inactive, __a, __p) __arm_vrev64q_m(__inactive, __a, __p) #define vqrdmlashq(__a, __b, __c) __arm_vqrdmlashq(__a, __b, __c) #define vqrdmlahq(__a, __b, __c) __arm_vqrdmlahq(__a, __b, __c) #define vqdmlashq(__a, __b, __c) __arm_vqdmlashq(__a, __b, __c) @@ -118,7 +114,6 @@ #define vrmlsldavhaq(__a, __b, __c) __arm_vrmlsldavhaq(__a, __b, __c) #define vrmlsldavhaxq(__a, __b, __c) __arm_vrmlsldavhaxq(__a, __b, __c) #define vaddlvaq_p(__a, __b, __p) __arm_vaddlvaq_p(__a, __b, __p) -#define vrev16q_m(__inactive, __a, __p) __arm_vrev16q_m(__inactive, __a, __p) #define vrmlaldavhq_p(__a, __b, __p) __arm_vrmlaldavhq_p(__a, __b, __p) #define vrmlaldavhxq_p(__a, __b, __p) __arm_vrmlaldavhxq_p(__a, __b, __p) #define vrmlsldavhq_p(__a, __b, __p) __arm_vrmlsldavhq_p(__a, __b, __p) @@ -133,7 +128,6 @@ #define vmlsldavxq_p(__a, __b, __p) __arm_vmlsldavxq_p(__a, __b, __p) #define vmovlbq_m(__inactive, __a, __p) __arm_vmovlbq_m(__inactive, __a, __p) #define vmovltq_m(__inactive, __a, __p) __arm_vmovltq_m(__inactive, __a, __p) -#define vrev32q_m(__inactive, __a, __p) __arm_vrev32q_m(__inactive, __a, __p) #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) #define vqshluq_m(__inactive, __a, __imm, __p) __arm_vqshluq_m(__inactive, __a, __imm, __p) #define vabavq_p(__a, __b, __c, __p) __arm_vabavq_p(__a, __b, __c, __p) @@ -264,9 +258,6 @@ #define vmovltq_x(__a, __p) __arm_vmovltq_x(__a, __p) #define vmvnq_x(__a, __p) __arm_vmvnq_x(__a, __p) #define vornq_x(__a, __b, __p) __arm_vornq_x(__a, __b, __p) -#define vrev16q_x(__a, __p) __arm_vrev16q_x(__a, __p) -#define vrev32q_x(__a, __p) __arm_vrev32q_x(__a, __p) -#define vrev64q_x(__a, __p) __arm_vrev64q_x(__a, __p) #define vadciq(__a, __b, __carry_out) __arm_vadciq(__a, __b, __carry_out) #define vadciq_m(__inactive, __a, __b, __carry_out, __p) __arm_vadciq_m(__inactive, __a, __b, __carry_out, __p) #define vadcq(__a, __b, __carry) __arm_vadcq(__a, __b, __carry) @@ -333,11 +324,8 @@ #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) -#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) -#define vrev64q_f32(__a) __arm_vrev64q_f32(__a) #define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) #define vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) -#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) #define vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) #define vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) #define vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) @@ -360,12 +348,6 @@ #define vmvnq_s32(__a) __arm_vmvnq_s32(__a) #define vmvnq_n_s16( __imm) __arm_vmvnq_n_s16( __imm) #define vmvnq_n_s32( __imm) __arm_vmvnq_n_s32( __imm) -#define vrev16q_s8(__a) __arm_vrev16q_s8(__a) -#define vrev32q_s8(__a) __arm_vrev32q_s8(__a) -#define vrev32q_s16(__a) __arm_vrev32q_s16(__a) -#define vrev64q_s8(__a) __arm_vrev64q_s8(__a) -#define vrev64q_s16(__a) __arm_vrev64q_s16(__a) -#define vrev64q_s32(__a) __arm_vrev64q_s32(__a) #define vcvtaq_s16_f16(__a) __arm_vcvtaq_s16_f16(__a) #define vcvtaq_s32_f32(__a) __arm_vcvtaq_s32_f32(__a) #define vcvtnq_s16_f16(__a) __arm_vcvtnq_s16_f16(__a) @@ -376,9 +358,6 @@ #define vcvtmq_s32_f32(__a) __arm_vcvtmq_s32_f32(__a) #define vcvtq_s16_f16(__a) __arm_vcvtq_s16_f16(__a) #define vcvtq_s32_f32(__a) __arm_vcvtq_s32_f32(__a) -#define vrev64q_u8(__a) __arm_vrev64q_u8(__a) -#define vrev64q_u16(__a) __arm_vrev64q_u16(__a) -#define vrev64q_u32(__a) __arm_vrev64q_u32(__a) #define vmvnq_u8(__a) __arm_vmvnq_u8(__a) #define vmvnq_u16(__a) __arm_vmvnq_u16(__a) #define vmvnq_u32(__a) __arm_vmvnq_u32(__a) @@ -388,15 +367,12 @@ #define vaddvq_u8(__a) __arm_vaddvq_u8(__a) #define vaddvq_u16(__a) __arm_vaddvq_u16(__a) #define vaddvq_u32(__a) __arm_vaddvq_u32(__a) -#define vrev32q_u8(__a) __arm_vrev32q_u8(__a) -#define vrev32q_u16(__a) __arm_vrev32q_u16(__a) #define vmovltq_u8(__a) __arm_vmovltq_u8(__a) #define vmovltq_u16(__a) __arm_vmovltq_u16(__a) #define vmovlbq_u8(__a) __arm_vmovlbq_u8(__a) #define vmovlbq_u16(__a) __arm_vmovlbq_u16(__a) #define vmvnq_n_u16( __imm) __arm_vmvnq_n_u16( __imm) #define vmvnq_n_u32( __imm) __arm_vmvnq_n_u32( __imm) -#define vrev16q_u8(__a) __arm_vrev16q_u8(__a) #define vaddlvq_u32(__a) __arm_vaddlvq_u32(__a) #define vcvtq_u16_f16(__a) __arm_vcvtq_u16_f16(__a) #define vcvtq_u32_f32(__a) __arm_vcvtq_u32_f32(__a) @@ -586,7 +562,6 @@ #define vabavq_u32(__a, __b, __c) __arm_vabavq_u32(__a, __b, __c) #define vpselq_u8(__a, __b, __p) __arm_vpselq_u8(__a, __b, __p) #define vpselq_s8(__a, __b, __p) __arm_vpselq_s8(__a, __b, __p) -#define vrev64q_m_u8(__inactive, __a, __p) __arm_vrev64q_m_u8(__inactive, __a, __p) #define vmvnq_m_u8(__inactive, __a, __p) __arm_vmvnq_m_u8(__inactive, __a, __p) #define vmlasq_n_u8(__a, __b, __c) __arm_vmlasq_n_u8(__a, __b, __c) #define vmlaq_n_u8(__a, __b, __c) __arm_vmlaq_n_u8(__a, __b, __c) @@ -596,7 +571,6 @@ #define vaddvaq_p_u8(__a, __b, __p) __arm_vaddvaq_p_u8(__a, __b, __p) #define vsriq_n_u8(__a, __b, __imm) __arm_vsriq_n_u8(__a, __b, __imm) #define vsliq_n_u8(__a, __b, __imm) __arm_vsliq_n_u8(__a, __b, __imm) -#define vrev64q_m_s8(__inactive, __a, __p) __arm_vrev64q_m_s8(__inactive, __a, __p) #define vmvnq_m_s8(__inactive, __a, __p) __arm_vmvnq_m_s8(__inactive, __a, __p) #define vmlsdavxq_p_s8(__a, __b, __p) __arm_vmlsdavxq_p_s8(__a, __b, __p) #define vmlsdavq_p_s8(__a, __b, __p) __arm_vmlsdavq_p_s8(__a, __b, __p) @@ -626,7 +600,6 @@ #define vsliq_n_s8(__a, __b, __imm) __arm_vsliq_n_s8(__a, __b, __imm) #define vpselq_u16(__a, __b, __p) __arm_vpselq_u16(__a, __b, __p) #define vpselq_s16(__a, __b, __p) __arm_vpselq_s16(__a, __b, __p) -#define vrev64q_m_u16(__inactive, __a, __p) __arm_vrev64q_m_u16(__inactive, __a, __p) #define vmvnq_m_u16(__inactive, __a, __p) __arm_vmvnq_m_u16(__inactive, __a, __p) #define vmlasq_n_u16(__a, __b, __c) __arm_vmlasq_n_u16(__a, __b, __c) #define vmlaq_n_u16(__a, __b, __c) __arm_vmlaq_n_u16(__a, __b, __c) @@ -636,7 +609,6 @@ #define vaddvaq_p_u16(__a, __b, __p) __arm_vaddvaq_p_u16(__a, __b, __p) #define vsriq_n_u16(__a, __b, __imm) __arm_vsriq_n_u16(__a, __b, __imm) #define vsliq_n_u16(__a, __b, __imm) __arm_vsliq_n_u16(__a, __b, __imm) -#define vrev64q_m_s16(__inactive, __a, __p) __arm_vrev64q_m_s16(__inactive, __a, __p) #define vmvnq_m_s16(__inactive, __a, __p) __arm_vmvnq_m_s16(__inactive, __a, __p) #define vmlsdavxq_p_s16(__a, __b, __p) __arm_vmlsdavxq_p_s16(__a, __b, __p) #define vmlsdavq_p_s16(__a, __b, __p) __arm_vmlsdavq_p_s16(__a, __b, __p) @@ -666,7 +638,6 @@ #define vsliq_n_s16(__a, __b, __imm) __arm_vsliq_n_s16(__a, __b, __imm) #define vpselq_u32(__a, __b, __p) __arm_vpselq_u32(__a, __b, __p) #define vpselq_s32(__a, __b, __p) __arm_vpselq_s32(__a, __b, __p) -#define vrev64q_m_u32(__inactive, __a, __p) __arm_vrev64q_m_u32(__inactive, __a, __p) #define vmvnq_m_u32(__inactive, __a, __p) __arm_vmvnq_m_u32(__inactive, __a, __p) #define vmlasq_n_u32(__a, __b, __c) __arm_vmlasq_n_u32(__a, __b, __c) #define vmlaq_n_u32(__a, __b, __c) __arm_vmlaq_n_u32(__a, __b, __c) @@ -676,7 +647,6 @@ #define vaddvaq_p_u32(__a, __b, __p) __arm_vaddvaq_p_u32(__a, __b, __p) #define vsriq_n_u32(__a, __b, __imm) __arm_vsriq_n_u32(__a, __b, __imm) #define vsliq_n_u32(__a, __b, __imm) __arm_vsliq_n_u32(__a, __b, __imm) -#define vrev64q_m_s32(__inactive, __a, __p) __arm_vrev64q_m_s32(__inactive, __a, __p) #define vmvnq_m_s32(__inactive, __a, __p) __arm_vmvnq_m_s32(__inactive, __a, __p) #define vmlsdavxq_p_s32(__a, __b, __p) __arm_vmlsdavxq_p_s32(__a, __b, __p) #define vmlsdavq_p_s32(__a, __b, __p) __arm_vmlsdavq_p_s32(__a, __b, __p) @@ -714,14 +684,11 @@ #define vcvtbq_m_f32_f16(__inactive, __a, __p) __arm_vcvtbq_m_f32_f16(__inactive, __a, __p) #define vcvttq_m_f16_f32(__a, __b, __p) __arm_vcvttq_m_f16_f32(__a, __b, __p) #define vcvttq_m_f32_f16(__inactive, __a, __p) __arm_vcvttq_m_f32_f16(__inactive, __a, __p) -#define vrev16q_m_s8(__inactive, __a, __p) __arm_vrev16q_m_s8(__inactive, __a, __p) -#define vrev32q_m_f16(__inactive, __a, __p) __arm_vrev32q_m_f16(__inactive, __a, __p) #define vrmlaldavhq_p_s32(__a, __b, __p) __arm_vrmlaldavhq_p_s32(__a, __b, __p) #define vrmlaldavhxq_p_s32(__a, __b, __p) __arm_vrmlaldavhxq_p_s32(__a, __b, __p) #define vrmlsldavhq_p_s32(__a, __b, __p) __arm_vrmlsldavhq_p_s32(__a, __b, __p) #define vrmlsldavhxq_p_s32(__a, __b, __p) __arm_vrmlsldavhxq_p_s32(__a, __b, __p) #define vaddlvaq_p_u32(__a, __b, __p) __arm_vaddlvaq_p_u32(__a, __b, __p) -#define vrev16q_m_u8(__inactive, __a, __p) __arm_vrev16q_m_u8(__inactive, __a, __p) #define vrmlaldavhq_p_u32(__a, __b, __p) __arm_vrmlaldavhq_p_u32(__a, __b, __p) #define vmvnq_m_n_s16(__inactive, __imm, __p) __arm_vmvnq_m_n_s16(__inactive, __imm, __p) #define vcmlaq_f16(__a, __b, __c) __arm_vcmlaq_f16(__a, __b, __c) @@ -748,8 +715,6 @@ #define vmovlbq_m_s8(__inactive, __a, __p) __arm_vmovlbq_m_s8(__inactive, __a, __p) #define vmovltq_m_s8(__inactive, __a, __p) __arm_vmovltq_m_s8(__inactive, __a, __p) #define vpselq_f16(__a, __b, __p) __arm_vpselq_f16(__a, __b, __p) -#define vrev32q_m_s8(__inactive, __a, __p) __arm_vrev32q_m_s8(__inactive, __a, __p) -#define vrev64q_m_f16(__inactive, __a, __p) __arm_vrev64q_m_f16(__inactive, __a, __p) #define vmvnq_m_n_u16(__inactive, __imm, __p) __arm_vmvnq_m_n_u16(__inactive, __imm, __p) #define vcvtmq_m_u16_f16(__inactive, __a, __p) __arm_vcvtmq_m_u16_f16(__inactive, __a, __p) #define vcvtnq_m_u16_f16(__inactive, __a, __p) __arm_vcvtnq_m_u16_f16(__inactive, __a, __p) @@ -759,7 +724,6 @@ #define vmlaldavq_p_u16(__a, __b, __p) __arm_vmlaldavq_p_u16(__a, __b, __p) #define vmovlbq_m_u8(__inactive, __a, __p) __arm_vmovlbq_m_u8(__inactive, __a, __p) #define vmovltq_m_u8(__inactive, __a, __p) __arm_vmovltq_m_u8(__inactive, __a, __p) -#define vrev32q_m_u8(__inactive, __a, __p) __arm_vrev32q_m_u8(__inactive, __a, __p) #define vmvnq_m_n_s32(__inactive, __imm, __p) __arm_vmvnq_m_n_s32(__inactive, __imm, __p) #define vcmlaq_f32(__a, __b, __c) __arm_vcmlaq_f32(__a, __b, __c) #define vcmlaq_rot180_f32(__a, __b, __c) __arm_vcmlaq_rot180_f32(__a, __b, __c) @@ -785,8 +749,6 @@ #define vmovlbq_m_s16(__inactive, __a, __p) __arm_vmovlbq_m_s16(__inactive, __a, __p) #define vmovltq_m_s16(__inactive, __a, __p) __arm_vmovltq_m_s16(__inactive, __a, __p) #define vpselq_f32(__a, __b, __p) __arm_vpselq_f32(__a, __b, __p) -#define vrev32q_m_s16(__inactive, __a, __p) __arm_vrev32q_m_s16(__inactive, __a, __p) -#define vrev64q_m_f32(__inactive, __a, __p) __arm_vrev64q_m_f32(__inactive, __a, __p) #define vmvnq_m_n_u32(__inactive, __imm, __p) __arm_vmvnq_m_n_u32(__inactive, __imm, __p) #define vcvtmq_m_u32_f32(__inactive, __a, __p) __arm_vcvtmq_m_u32_f32(__inactive, __a, __p) #define vcvtnq_m_u32_f32(__inactive, __a, __p) __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) @@ -796,7 +758,6 @@ #define vmlaldavq_p_u32(__a, __b, __p) __arm_vmlaldavq_p_u32(__a, __b, __p) #define vmovlbq_m_u16(__inactive, __a, __p) __arm_vmovlbq_m_u16(__inactive, __a, __p) #define vmovltq_m_u16(__inactive, __a, __p) __arm_vmovltq_m_u16(__inactive, __a, __p) -#define vrev32q_m_u16(__inactive, __a, __p) __arm_vrev32q_m_u16(__inactive, __a, __p) #define vsriq_m_n_s8(__a, __b, __imm, __p) __arm_vsriq_m_n_s8(__a, __b, __imm, __p) #define vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) #define vqshluq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s8(__inactive, __a, __imm, __p) @@ -1372,18 +1333,6 @@ #define vornq_x_u8(__a, __b, __p) __arm_vornq_x_u8(__a, __b, __p) #define vornq_x_u16(__a, __b, __p) __arm_vornq_x_u16(__a, __b, __p) #define vornq_x_u32(__a, __b, __p) __arm_vornq_x_u32(__a, __b, __p) -#define vrev16q_x_s8(__a, __p) __arm_vrev16q_x_s8(__a, __p) -#define vrev16q_x_u8(__a, __p) __arm_vrev16q_x_u8(__a, __p) -#define vrev32q_x_s8(__a, __p) __arm_vrev32q_x_s8(__a, __p) -#define vrev32q_x_s16(__a, __p) __arm_vrev32q_x_s16(__a, __p) -#define vrev32q_x_u8(__a, __p) __arm_vrev32q_x_u8(__a, __p) -#define vrev32q_x_u16(__a, __p) __arm_vrev32q_x_u16(__a, __p) -#define vrev64q_x_s8(__a, __p) __arm_vrev64q_x_s8(__a, __p) -#define vrev64q_x_s16(__a, __p) __arm_vrev64q_x_s16(__a, __p) -#define vrev64q_x_s32(__a, __p) __arm_vrev64q_x_s32(__a, __p) -#define vrev64q_x_u8(__a, __p) __arm_vrev64q_x_u8(__a, __p) -#define vrev64q_x_u16(__a, __p) __arm_vrev64q_x_u16(__a, __p) -#define vrev64q_x_u32(__a, __p) __arm_vrev64q_x_u32(__a, __p) #define vdupq_x_n_f16(__a, __p) __arm_vdupq_x_n_f16(__a, __p) #define vdupq_x_n_f32(__a, __p) __arm_vdupq_x_n_f32(__a, __p) #define vcaddq_rot90_x_f16(__a, __b, __p) __arm_vcaddq_rot90_x_f16(__a, __b, __p) @@ -1438,9 +1387,6 @@ #define vbrsrq_x_n_f32(__a, __b, __p) __arm_vbrsrq_x_n_f32(__a, __b, __p) #define vornq_x_f16(__a, __b, __p) __arm_vornq_x_f16(__a, __b, __p) #define vornq_x_f32(__a, __b, __p) __arm_vornq_x_f32(__a, __b, __p) -#define vrev32q_x_f16(__a, __p) __arm_vrev32q_x_f16(__a, __p) -#define vrev64q_x_f16(__a, __p) __arm_vrev64q_x_f16(__a, __p) -#define vrev64q_x_f32(__a, __p) __arm_vrev64q_x_f32(__a, __p) #define vadciq_s32(__a, __b, __carry_out) __arm_vadciq_s32(__a, __b, __carry_out) #define vadciq_u32(__a, __b, __carry_out) __arm_vadciq_u32(__a, __b, __carry_out) #define vadciq_m_s32(__inactive, __a, __b, __carry_out, __p) __arm_vadciq_m_s32(__inactive, __a, __b, __carry_out, __p) @@ -1719,69 +1665,6 @@ __arm_vmvnq_n_s32 (const int32_t __imm) return __builtin_mve_vmvnq_n_sv4si (__imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_s8 (int8x16_t __a) -{ - return __builtin_mve_vrev16q_sv16qi (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_s8 (int8x16_t __a) -{ - return __builtin_mve_vrev32q_sv16qi (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_s16 (int16x8_t __a) -{ - return __builtin_mve_vrev32q_sv8hi (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_s8 (int8x16_t __a) -{ - return __builtin_mve_vrev64q_sv16qi (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_s16 (int16x8_t __a) -{ - return __builtin_mve_vrev64q_sv8hi (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_s32 (int32x4_t __a) -{ - return __builtin_mve_vrev64q_sv4si (__a); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_u8 (uint8x16_t __a) -{ - return __builtin_mve_vrev64q_uv16qi (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_u16 (uint16x8_t __a) -{ - return __builtin_mve_vrev64q_uv8hi (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_u32 (uint32x4_t __a) -{ - return __builtin_mve_vrev64q_uv4si (__a); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_u8 (uint8x16_t __a) @@ -1845,20 +1728,6 @@ __arm_vaddvq_u32 (uint32x4_t __a) return __builtin_mve_vaddvq_uv4si (__a); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_u8 (uint8x16_t __a) -{ - return __builtin_mve_vrev32q_uv16qi (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_u16 (uint16x8_t __a) -{ - return __builtin_mve_vrev32q_uv8hi (__a); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmovltq_u8 (uint8x16_t __a) @@ -1901,13 +1770,6 @@ __arm_vmvnq_n_u32 (const int __imm) return __builtin_mve_vmvnq_n_uv4si (__imm); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_u8 (uint8x16_t __a) -{ - return __builtin_mve_vrev16q_uv16qi (__a); -} - __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vaddlvq_u32 (uint32x4_t __a) @@ -2927,13 +2789,6 @@ __arm_vpselq_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv16qi (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv16qi (__inactive, __a, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) @@ -2997,13 +2852,6 @@ __arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv16qi (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) @@ -3207,13 +3055,6 @@ __arm_vpselq_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv8hi (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) @@ -3277,13 +3118,6 @@ __arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv8hi (__inactive, __a, __p); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) @@ -3487,13 +3321,6 @@ __arm_vpselq_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_sv4si (__a, __b, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv4si (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) @@ -3557,13 +3384,6 @@ __arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv4si (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) @@ -3795,13 +3615,6 @@ __arm_vaddlvaq_p_s32 (int64_t __a, int32x4_t __b, mve_pred16_t __p) return __builtin_mve_vaddlvaq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev16q_m_sv16qi (__inactive, __a, __p); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) @@ -3837,13 +3650,6 @@ __arm_vaddlvaq_p_u32 (uint64_t __a, uint32x4_t __b, mve_pred16_t __p) return __builtin_mve_vaddlvaq_p_uv4si (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev16q_m_uv16qi (__inactive, __a, __p); -} - __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhq_p_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) @@ -3928,13 +3734,6 @@ __arm_vmovltq_m_s8 (int16x8_t __inactive, int8x16_t __a, mve_pred16_t __p) return __builtin_mve_vmovltq_m_sv16qi (__inactive, __a, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_sv16qi (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_n_u16 (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) @@ -3970,13 +3769,6 @@ __arm_vmovltq_m_u8 (uint16x8_t __inactive, uint8x16_t __a, mve_pred16_t __p) return __builtin_mve_vmovltq_m_uv16qi (__inactive, __a, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_uv16qi (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_n_s32 (int32x4_t __inactive, const int __imm, mve_pred16_t __p) @@ -4054,13 +3846,6 @@ __arm_vmovltq_m_s16 (int32x4_t __inactive, int16x8_t __a, mve_pred16_t __p) return __builtin_mve_vmovltq_m_sv8hi (__inactive, __a, __p); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_sv8hi (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m_n_u32 (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) @@ -4096,13 +3881,6 @@ __arm_vmovltq_m_u16 (uint32x4_t __inactive, uint16x8_t __a, mve_pred16_t __p) return __builtin_mve_vmovltq_m_uv8hi (__inactive, __a, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_uv8hi (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -7659,90 +7437,6 @@ __arm_vornq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) return __builtin_mve_vornq_m_uv4si (__arm_vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_x_s8 (int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev16q_m_sv16qi (__arm_vuninitializedq_s8 (), __a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_x_u8 (uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev16q_m_uv16qi (__arm_vuninitializedq_u8 (), __a, __p); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x_s8 (int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_sv16qi (__arm_vuninitializedq_s8 (), __a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x_s16 (int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_sv8hi (__arm_vuninitializedq_s16 (), __a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x_u8 (uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_uv16qi (__arm_vuninitializedq_u8 (), __a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x_u16 (uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_uv8hi (__arm_vuninitializedq_u16 (), __a, __p); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_s8 (int8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv16qi (__arm_vuninitializedq_s8 (), __a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_s16 (int16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv8hi (__arm_vuninitializedq_s16 (), __a, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_s32 (int32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_sv4si (__arm_vuninitializedq_s32 (), __a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_u8 (uint8x16_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv16qi (__arm_vuninitializedq_u8 (), __a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_u16 (uint16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv8hi (__arm_vuninitializedq_u16 (), __a, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_u32 (uint32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_uv4si (__arm_vuninitializedq_u32 (), __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadciq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) @@ -8463,20 +8157,6 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) __builtin_mve_vst4qv4sf (__addr, __rv.__o); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f16 (float16x8_t __a) -{ - return __builtin_mve_vrev64q_fv8hf (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f32 (float32x4_t __a) -{ - return __builtin_mve_vrev64q_fv4sf (__a); -} - __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vdupq_n_f16 (float16_t __a) @@ -8491,13 +8171,6 @@ __arm_vdupq_n_f32 (float32_t __a) return __builtin_mve_vdupq_n_fv4sf (__a); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_f16 (float16x8_t __a) -{ - return __builtin_mve_vrev32q_fv8hf (__a); -} - __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvttq_f32_f16 (float16x8_t __a) @@ -8961,13 +8634,6 @@ __arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __ return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p); -} - __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) @@ -9066,13 +8732,6 @@ __arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_fv8hf (__a, __b, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) @@ -9199,13 +8858,6 @@ __arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) return __builtin_mve_vpselq_fv4sf (__a, __b, __p); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) @@ -10164,27 +9816,6 @@ __arm_vornq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) return __builtin_mve_vornq_m_fv4sf (__arm_vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x_f16 (float16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev32q_m_fv8hf (__arm_vuninitializedq_f16 (), __a, __p); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_f16 (float16x8_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_fv8hf (__arm_vuninitializedq_f16 (), __a, __p); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x_f32 (float32x4_t __a, mve_pred16_t __p) -{ - return __builtin_mve_vrev64q_m_fv4sf (__arm_vuninitializedq_f32 (), __a, __p); -} - __extension__ extern __inline float16x8x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vld4q_f16 (float16_t const * __addr) @@ -10443,69 +10074,6 @@ __arm_vmvnq (int32x4_t __a) return __arm_vmvnq_s32 (__a); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q (int8x16_t __a) -{ - return __arm_vrev16q_s8 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q (int8x16_t __a) -{ - return __arm_vrev32q_s8 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q (int16x8_t __a) -{ - return __arm_vrev32q_s16 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (int8x16_t __a) -{ - return __arm_vrev64q_s8 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (int16x8_t __a) -{ - return __arm_vrev64q_s16 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (int32x4_t __a) -{ - return __arm_vrev64q_s32 (__a); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (uint8x16_t __a) -{ - return __arm_vrev64q_u8 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (uint16x8_t __a) -{ - return __arm_vrev64q_u16 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (uint32x4_t __a) -{ - return __arm_vrev64q_u32 (__a); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq (uint8x16_t __a) @@ -10569,20 +10137,6 @@ __arm_vaddvq (uint32x4_t __a) return __arm_vaddvq_u32 (__a); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q (uint8x16_t __a) -{ - return __arm_vrev32q_u8 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q (uint16x8_t __a) -{ - return __arm_vrev32q_u16 (__a); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmovltq (uint8x16_t __a) @@ -10611,13 +10165,6 @@ __arm_vmovlbq (uint16x8_t __a) return __arm_vmovlbq_u16 (__a); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q (uint8x16_t __a) -{ - return __arm_vrev16q_u8 (__a); -} - __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vaddlvq (uint32x4_t __a) @@ -11556,13 +11103,6 @@ __arm_vpselq (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) return __arm_vpselq_s8 (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_u8 (__inactive, __a, __p); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) @@ -11626,13 +11166,6 @@ __arm_vsliq (uint8x16_t __a, uint8x16_t __b, const int __imm) return __arm_vsliq_n_u8 (__a, __b, __imm); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_s8 (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) @@ -11836,13 +11369,6 @@ __arm_vpselq (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) return __arm_vpselq_s16 (__a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_u16 (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) @@ -11906,13 +11432,6 @@ __arm_vsliq (uint16x8_t __a, uint16x8_t __b, const int __imm) return __arm_vsliq_n_u16 (__a, __b, __imm); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_s16 (__inactive, __a, __p); -} - __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) @@ -12116,13 +11635,6 @@ __arm_vpselq (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) return __arm_vpselq_s32 (__a, __b, __p); } -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_u32 (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) @@ -12186,13 +11698,6 @@ __arm_vsliq (uint32x4_t __a, uint32x4_t __b, const int __imm) return __arm_vsliq_n_u32 (__a, __b, __imm); } -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_s32 (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) @@ -12424,13 +11929,6 @@ __arm_vaddlvaq_p (int64_t __a, int32x4_t __b, mve_pred16_t __p) return __arm_vaddlvaq_p_s32 (__a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_m (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev16q_m_s8 (__inactive, __a, __p); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhq_p (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) @@ -12466,13 +11964,6 @@ __arm_vaddlvaq_p (uint64_t __a, uint32x4_t __b, mve_pred16_t __p) return __arm_vaddlvaq_p_u32 (__a, __b, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_m (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev16q_m_u8 (__inactive, __a, __p); -} - __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhq_p (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) @@ -12557,13 +12048,6 @@ __arm_vmovltq_m (int16x8_t __inactive, int8x16_t __a, mve_pred16_t __p) return __arm_vmovltq_m_s8 (__inactive, __a, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_m_s8 (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) @@ -12599,13 +12083,6 @@ __arm_vmovltq_m (uint16x8_t __inactive, uint8x16_t __a, mve_pred16_t __p) return __arm_vmovltq_m_u8 (__inactive, __a, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_m_u8 (__inactive, __a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (int32x4_t __inactive, const int __imm, mve_pred16_t __p) @@ -12683,13 +12160,6 @@ __arm_vmovltq_m (int32x4_t __inactive, int16x8_t __a, mve_pred16_t __p) return __arm_vmovltq_m_s16 (__inactive, __a, __p); } -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_m_s16 (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_m (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) @@ -12725,13 +12195,6 @@ __arm_vmovltq_m (uint32x4_t __inactive, uint16x8_t __a, mve_pred16_t __p) return __arm_vmovltq_m_u16 (__inactive, __a, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_m_u16 (__inactive, __a, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vsriq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) @@ -15791,90 +15254,6 @@ __arm_vornq_x (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) return __arm_vornq_x_u32 (__a, __b, __p); } -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_x (int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev16q_x_s8 (__a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev16q_x (uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev16q_x_u8 (__a, __p); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x (int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_x_s8 (__a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x (int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_x_s16 (__a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x (uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_x_u8 (__a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x (uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_x_u16 (__a, __p); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (int8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_s8 (__a, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (int16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_s16 (__a, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (int32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_s32 (__a, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (uint8x16_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_u8 (__a, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (uint16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_u16 (__a, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (uint32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_u32 (__a, __p); -} - __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vadciq (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) @@ -16367,20 +15746,6 @@ __arm_vst4q (float32_t * __addr, float32x4x4_t __value) __arm_vst4q_f32 (__addr, __value); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (float16x8_t __a) -{ - return __arm_vrev64q_f16 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q (float32x4_t __a) -{ - return __arm_vrev64q_f32 (__a); -} - __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vdupq_n (float16_t __a) @@ -16395,13 +15760,6 @@ __arm_vdupq_n (float32_t __a) return __arm_vdupq_n_f32 (__a); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q (float16x8_t __a) -{ - return __arm_vrev32q_f16 (__a); -} - __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvttq_f32 (float16x8_t __a) @@ -16682,13 +16040,6 @@ __arm_vcvttq_m (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) return __arm_vcvttq_m_f32_f16 (__inactive, __a, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_m_f16 (__inactive, __a, __p); -} - __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq (float16x8_t __a, float16x8_t __b, float16x8_t __c) @@ -16787,13 +16138,6 @@ __arm_vpselq (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) return __arm_vpselq_f16 (__a, __b, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_f16 (__inactive, __a, __p); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvtmq_m (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) @@ -16920,13 +16264,6 @@ __arm_vpselq (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) return __arm_vpselq_f32 (__a, __b, __p); } -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_m_f32 (__inactive, __a, __p); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcvtmq_m (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) @@ -17627,27 +16964,6 @@ __arm_vornq_x (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) return __arm_vornq_x_f32 (__a, __b, __p); } -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_x (float16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev32q_x_f16 (__a, __p); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (float16x8_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_f16 (__a, __p); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_x (float32x4_t __a, mve_pred16_t __p) -{ - return __arm_vrev64q_x_f32 (__a, __p); -} - __extension__ extern __inline float16x8x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vld4q (float16_t const * __addr) @@ -18021,30 +17337,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) -#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - #define __arm_vdupq_n(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vdupq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vdupq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) -#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) - #define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) @@ -18053,11 +17350,6 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) -#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) - #define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ @@ -18557,27 +17849,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));}) -#define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev64q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev64q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrev64q_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev64q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev64q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrev64q_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrev64q_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrev64q_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) - -#define __arm_vrev32q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev32q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev32q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrev32q_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2));}) - #define __arm_vpselq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -18592,12 +17863,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vpselq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vpselq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) - #define __arm_vbicq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -19144,25 +18409,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2));}) - -#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) - #define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ @@ -19240,27 +18486,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) -#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) - -#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) - -#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) - #define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ @@ -19420,16 +18645,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev64q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev64q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrev64q_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev64q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev64q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrev64q_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -19582,20 +18797,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) -#define __arm_vrev32q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev32q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev32q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) - -#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) - #define __arm_vmovltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -19994,22 +19195,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));}) - -#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vbicq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ @@ -20090,11 +19275,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define __arm_vrev16q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2));}) - #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \