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(VSHLLBQ_N, VSHLLTQ_N): Remove. (VSHLLxQ_N): New. (VSHLLBQ_M_N, VSHLLTQ_M_N): Remove. (VSHLLxQ_M_N): New. * config/arm/mve.md (mve_vshllbq_n_) (mve_vshlltq_n_): Merge into ... (@mve_q_n_): ... this. (mve_vshllbq_m_n_, mve_vshlltq_m_n_): Merge into ... (@mve_q_m_n_): ... this. --- gcc/config/arm/iterators.md | 10 +++++--- gcc/config/arm/mve.md | 50 ++++++++----------------------------- 2 files changed, 16 insertions(+), 44 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 20735284979..e82ff0d5d9b 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -731,6 +731,10 @@ (define_int_attr mve_insn [ (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt") (VRSHRQ_M_N_S "vrshr") (VRSHRQ_M_N_U "vrshr") (VRSHRQ_N_S "vrshr") (VRSHRQ_N_U "vrshr") + (VSHLLBQ_M_N_S "vshllb") (VSHLLBQ_M_N_U "vshllb") + (VSHLLBQ_N_S "vshllb") (VSHLLBQ_N_U "vshllb") + (VSHLLTQ_M_N_S "vshllt") (VSHLLTQ_M_N_U "vshllt") + (VSHLLTQ_N_S "vshllt") (VSHLLTQ_N_U "vshllt") (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl") (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl") (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl") @@ -2133,8 +2137,7 @@ (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S]) (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S]) -(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U]) -(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S]) +(define_int_iterator VSHLLxQ_N [VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_S VSHLLTQ_N_U]) (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U]) (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U]) @@ -2250,8 +2253,7 @@ (define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S]) (define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U]) (define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S]) (define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S]) -(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S]) -(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) +(define_int_iterator VSHLLxQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 2273078807b..98728e6f3ef 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1830,32 +1830,18 @@ (define_insn "mve_vrmlsldavhxq_sv4si" ]) ;; -;; [vshllbq_n_s, vshllbq_n_u]) +;; [vshllbq_n_s, vshllbq_n_u] +;; [vshlltq_n_u, vshlltq_n_s] ;; -(define_insn "mve_vshllbq_n_" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] - VSHLLBQ_N)) - ] - "TARGET_HAVE_MVE" - "vshllb.%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vshlltq_n_u, vshlltq_n_s]) -;; -(define_insn "mve_vshlltq_n_" +(define_insn "@mve_q_n_" [ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") (match_operand:SI 2 "immediate_operand" "i")] - VSHLLTQ_N)) + VSHLLxQ_N)) ] "TARGET_HAVE_MVE" - "vshllt.%#\t%q0, %q1, %2" + ".%#\t%q0, %q1, %2" [(set_attr "type" "mve_move") ]) @@ -4410,36 +4396,20 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si" (set_attr "length""8")]) ;; -;; [vshllbq_m_n_u, vshllbq_m_n_s]) -;; -(define_insn "mve_vshllbq_m_n_" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_3 2 "s_register_operand" "w") - (match_operand:SI 3 "immediate_operand" "i") - (match_operand: 4 "vpr_register_operand" "Up")] - VSHLLBQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vshllbt.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vshlltq_m_n_u, vshlltq_m_n_s]) +;; [vshllbq_m_n_u, vshllbq_m_n_s] +;; [vshlltq_m_n_u, vshlltq_m_n_s] ;; -(define_insn "mve_vshlltq_m_n_" +(define_insn "@mve_q_m_n_" [ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") (match_operand: 4 "vpr_register_operand" "Up")] - VSHLLTQ_M_N)) + VSHLLxQ_M_N)) ] "TARGET_HAVE_MVE" - "vpst\;vshlltt.%#\t%q0, %q2, %3" + "vpst\;t.%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")])