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Fri, 5 May 2023 08:39:47 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 04/23] arm: [MVE intrinsics] factorize vqshlq vshlq Date: Fri, 5 May 2023 10:39:11 +0200 Message-ID: <20230505083930.101210-4-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505083930.101210-1-christophe.lyon@arm.com> References: <20230505083930.101210-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT021:EE_|AS2PR08MB9942:EE_|DBAEUR03FT052:EE_|AS8PR08MB8369:EE_ X-MS-Office365-Filtering-Correlation-Id: 2593f8b5-23c6-4694-0f43-08db4d4451ed x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Nnb4NoBvg9p2sseH6fg5f4l+tEs03z1Z0k9uypHXxZOaRgszmCKJlOHJb3KExvWIWMmFJYnew0yZZYn46AKSgWMh1+Mm3JBwB221QG4ATRCbBnRXbgsQMOH9x700W+V8BLzZ1f16dMrBU45ztNTLWHvCFYXumiFnxJgeSQckcOmfRsbJcO0nN+l1hUVdfQfnKKgV9FXC2FhMpVYPA83OHEdKza15t8/SjuxOKdmr/T/02X/GplPo9h7XHWOY0xJg+ha1XYUTJonga894AaxkWYh6N6pUNzcNsGPKqLKif8REQifzXVegVrZBPCwNqoCx/clQJysDDcykUZpPAeUX3n2Vxo5XpKJzqW3IIox36TfTyEhhSCmn3LHFFoXxWv+icLiWFMcs9tQS7sYQGTFlwHfCqEVKqsyQnZzxH7tk+8oXrTBqmJ+j5o0RwMIUosEZ1S473BDnXn18e0U65GJQESjSbVWY1zOwExQdaBPU91nx6rWx5Q6jXnLvla2DybLtjetQUe+vhcqf0qCaZ+Oe1VsXmLR3yQg2sG8Gwivoe0BbS2/nnpC/R1GxwSX4T4EIJkgeFLTt7gERiSywYbz4ustGxkk50/LumhhcE2dDwWFoxLsIOlymxg+ppsF5BElNeGrqtGt69FPlF+acykpIIp0YIdmDpT1eQ7KzvjSNMwLmtn9IfltV62S2WcqCSsxaGNvO7IGhMKGyqn4Ssz1EuhiF7vXyIG+F8dpm3t7u3x5rzsgaC6Ga082nPptH23MLltub6ZliCQalku6b52pkwKFNzgNMWdJCAlym3RJciDYAqXT4hqxWUja/YERgAhiH X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT052.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8369 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Factorize vqshlq and vshlq so that they use the same pattern. 2022-09-08 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N) (MVE_SHIFT_N, MVE_SHIFT_R): New. (mve_insn): Add vqshl, vshl. * config/arm/mve.md (mve_vqshlq_n_) (mve_vshlq_n_): Merge into ... (@mve_q_n_): ... this. (mve_vqshlq_r_, mve_vshlq_r_): Merge into ... (@mve_q_r_): ... this. (mve_vqshlq_m_r_, mve_vshlq_m_r_): Merge into ... (@mve_q_m_r_): ... this. (mve_vqshlq_m_n_, mve_vshlq_m_n_): Merge into ... (@mve_q_m_n_): ... this. * config/arm/vec-common.md (mve_vshlq_): Transform into ... (@mve_q_): ... this. --- gcc/config/arm/iterators.md | 29 +++++++++++ gcc/config/arm/mve.md | 99 ++++++++---------------------------- gcc/config/arm/vec-common.md | 4 +- 3 files changed, 51 insertions(+), 81 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index e7622fe752a..c53b42a86e9 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -435,6 +435,26 @@ (define_int_iterator MVE_INT_N_BINARY_LOGIC [ VORRQ_N_S VORRQ_N_U ]) +(define_int_iterator MVE_SHIFT_M_R [ + VQSHLQ_M_R_S VQSHLQ_M_R_U + VSHLQ_M_R_S VSHLQ_M_R_U + ]) + +(define_int_iterator MVE_SHIFT_M_N [ + VQSHLQ_M_N_S VQSHLQ_M_N_U + VSHLQ_M_N_S VSHLQ_M_N_U + ]) + +(define_int_iterator MVE_SHIFT_N [ + VQSHLQ_N_S VQSHLQ_N_U + VSHLQ_N_S VSHLQ_N_U + ]) + +(define_int_iterator MVE_SHIFT_R [ + VQSHLQ_R_S VQSHLQ_R_U + VSHLQ_R_S VSHLQ_R_U + ]) + (define_int_iterator MVE_RSHIFT_M_N [ VQRSHLQ_M_N_S VQRSHLQ_M_N_U VRSHLQ_M_N_S VRSHLQ_M_N_U @@ -540,7 +560,11 @@ (define_int_attr mve_insn [ (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl") (VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl") (VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl") + (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl") + (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl") (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl") + (VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl") + (VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl") (VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl") (VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub") (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub") @@ -554,7 +578,12 @@ (define_int_attr mve_insn [ (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl") (VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl") (VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl") + (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl") + (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl") (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl") + (VSHLQ_N_S "vshl") (VSHLQ_N_U "vshl") + (VSHLQ_R_S "vshl") (VSHLQ_R_U "vshl") + (VSHLQ_S "vshl") (VSHLQ_U "vshl") (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub") (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub") (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0d3343b6e29..fb1076aef73 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1389,32 +1389,34 @@ (define_insn "@mve_q_n_" ]) ;; -;; [vqshlq_n_s, vqshlq_n_u]) +;; [vqshlq_n_s, vqshlq_n_u] +;; [vshlq_n_u, vshlq_n_s] ;; -(define_insn "mve_vqshlq_n_" +(define_insn "@mve_q_n_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:SI 2 "immediate_operand" "i")] - VQSHLQ_N)) + MVE_SHIFT_N)) ] "TARGET_HAVE_MVE" - "vqshl.%#\t%q0, %q1, %2" + ".%#\t%q0, %q1, %2" [(set_attr "type" "mve_move") ]) ;; -;; [vqshlq_r_u, vqshlq_r_s]) +;; [vqshlq_r_u, vqshlq_r_s] +;; [vshlq_r_s, vshlq_r_u] ;; -(define_insn "mve_vqshlq_r_" +(define_insn "@mve_q_r_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r")] - VQSHLQ_R)) + MVE_SHIFT_R)) ] "TARGET_HAVE_MVE" - "vqshl.%#\t%q0, %2" + ".%#\t%q0, %2" [(set_attr "type" "mve_move") ]) @@ -1448,36 +1450,6 @@ (define_insn "mve_vrshrq_n_" [(set_attr "type" "mve_move") ]) -;; -;; [vshlq_n_u, vshlq_n_s]) -;; -(define_insn "mve_vshlq_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] - VSHLQ_N)) - ] - "TARGET_HAVE_MVE" - "vshl.%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vshlq_r_s, vshlq_r_u]) -;; -(define_insn "mve_vshlq_r_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:SI 2 "s_register_operand" "r")] - VSHLQ_R)) - ] - "TARGET_HAVE_MVE" - "vshl.%#\t%q0, %2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vabdq_f]) ;; @@ -3101,18 +3073,19 @@ (define_insn "@mve_q_m_n_" (set_attr "length""8")]) ;; -;; [vqshlq_m_r_u, vqshlq_m_r_s]) +;; [vqshlq_m_r_u, vqshlq_m_r_s] +;; [vshlq_m_r_u, vshlq_m_r_s] ;; -(define_insn "mve_vqshlq_m_r_" +(define_insn "@mve_q_m_r_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r") (match_operand: 3 "vpr_register_operand" "Up")] - VQSHLQ_M_R)) + MVE_SHIFT_M_R)) ] "TARGET_HAVE_MVE" - "vpst\;vqshlt.%#\t%q0, %2" + "vpst\;t.%#\t%q0, %2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -3132,22 +3105,6 @@ (define_insn "mve_vrev64q_m_" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vshlq_m_r_u, vshlq_m_r_s]) -;; -(define_insn "mve_vshlq_m_r_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:SI 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VSHLQ_M_R)) - ] - "TARGET_HAVE_MVE" - "vpst\;vshlt.%#\t%q0, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vsliq_n_u, vsliq_n_s]) ;; @@ -4881,19 +4838,20 @@ (define_insn "mve_vornq_m_" (set_attr "length""8")]) ;; -;; [vqshlq_m_n_s, vqshlq_m_n_u]) +;; [vqshlq_m_n_s, vqshlq_m_n_u] +;; [vshlq_m_n_s, vshlq_m_n_u] ;; -(define_insn "mve_vqshlq_m_n_" +(define_insn "@mve_q_m_n_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") (match_operand: 4 "vpr_register_operand" "Up")] - VQSHLQ_M_N)) + MVE_SHIFT_M_N)) ] "TARGET_HAVE_MVE" - "vpst\;vqshlt.%#\t%q0, %q2, %3" + "vpst\;t.%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -4914,23 +4872,6 @@ (define_insn "mve_vrshrq_m_n_" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vshlq_m_n_s, vshlq_m_n_u]) -;; -(define_insn "mve_vshlq_m_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "immediate_operand" "i") - (match_operand: 4 "vpr_register_operand" "Up")] - VSHLQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vshlt.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vshrq_m_n_s, vshrq_m_n_u]) ;; diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 918338ca5c0..b5fc86fdf28 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -357,14 +357,14 @@ (define_expand "@movmisalign" } }) -(define_insn "mve_vshlq_" +(define_insn "@mve_q_" [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w") (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")] VSHLQ))] "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" "@ - vshl.%#\t%0, %1, %2 + .%#\t%0, %1, %2 * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], mode, VALID_NEON_QREG_MODE (mode), true);" [(set_attr "type" "neon_shift_reg, neon_shift_imm")] )