diff mbox series

[06/11] riscv: Define Xmode macro

Message ID 20230428061210.2988035-7-christoph.muellner@vrull.eu
State Committed
Commit a3480aacc4ab01651725a63e05829a43bc23d549
Delegated to: Kito Cheng
Headers
Series Improvements for XThead* support |

Commit Message

Christoph Müllner April 28, 2023, 6:12 a.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).

gcc/ChangeLog:

	* config/riscv/riscv.h (Xmode): New macro.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv.h | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Kito Cheng April 28, 2023, 7:23 a.m. UTC | #1 
My first impression is that it should be the same as Pmode, but I
admit it has more clear semantics, and would be useful when we have
ilp32 on rv64.

So LGTM

On Fri, Apr 28, 2023 at 2:16 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> Define a Xmode macro that specifies the registers size (XLEN)
> similar to Pmode. This allows the backend code to write generic
> RV32/RV64 C code (under certain circumstances).
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.h (Xmode): New macro.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 66fb07d6652..90746fe14e3 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -791,6 +791,10 @@ typedef struct {
>
>  #define Pmode word_mode
>
> +/* Specify the machine mode that registers have.  */
> +
> +#define Xmode (TARGET_64BIT ? DImode : SImode)
> +
>  /* Give call MEMs SImode since it is the "most permissive" mode
>     for both 32-bit and 64-bit targets.  */
>
> --
> 2.40.1
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..90746fe14e3 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -791,6 +791,10 @@  typedef struct {
 
 #define Pmode word_mode
 
+/* Specify the machine mode that registers have.  */
+
+#define Xmode (TARGET_64BIT ? DImode : SImode)
+
 /* Give call MEMs SImode since it is the "most permissive" mode
    for both 32-bit and 64-bit targets.  */