Message ID | 20230428061210.2988035-7-christoph.muellner@vrull.eu |
---|---|
State | Committed |
Commit | a3480aacc4ab01651725a63e05829a43bc23d549 |
Delegated to: | Kito Cheng |
Headers |
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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:21 -0700 (PDT) From: Christoph Muellner <christoph.muellner@vrull.eu> To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>, Jim Wilson <jim.wilson.gcc@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Andrew Waterman <andrew@sifive.com>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Cooper Qu <cooper.qu@linux.alibaba.com>, Lifang Xia <lifang_xia@linux.alibaba.com>, Yunhai Shang <yunhai@linux.alibaba.com>, Zhiwei Liu <zhiwei_liu@linux.alibaba.com> Cc: =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu> Subject: [PATCH 06/11] riscv: Define Xmode macro Date: Fri, 28 Apr 2023 08:12:07 +0200 Message-Id: <20230428061210.2988035-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
Improvements for XThead* support
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Commit Message
Christoph Müllner
April 28, 2023, 6:12 a.m. UTC
From: Christoph Müllner <christoph.muellner@vrull.eu> Define a Xmode macro that specifies the registers size (XLEN) similar to Pmode. This allows the backend code to write generic RV32/RV64 C code (under certain circumstances). gcc/ChangeLog: * config/riscv/riscv.h (Xmode): New macro. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- gcc/config/riscv/riscv.h | 4 ++++ 1 file changed, 4 insertions(+)
Comments
My first impression is that it should be the same as Pmode, but I admit it has more clear semantics, and would be useful when we have ilp32 on rv64. So LGTM On Fri, Apr 28, 2023 at 2:16 PM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > Define a Xmode macro that specifies the registers size (XLEN) > similar to Pmode. This allows the backend code to write generic > RV32/RV64 C code (under certain circumstances). > > gcc/ChangeLog: > > * config/riscv/riscv.h (Xmode): New macro. > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> > --- > gcc/config/riscv/riscv.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 66fb07d6652..90746fe14e3 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -791,6 +791,10 @@ typedef struct { > > #define Pmode word_mode > > +/* Specify the machine mode that registers have. */ > + > +#define Xmode (TARGET_64BIT ? DImode : SImode) > + > /* Give call MEMs SImode since it is the "most permissive" mode > for both 32-bit and 64-bit targets. */ > > -- > 2.40.1 >
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 66fb07d6652..90746fe14e3 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -791,6 +791,10 @@ typedef struct { #define Pmode word_mode +/* Specify the machine mode that registers have. */ + +#define Xmode (TARGET_64BIT ? DImode : SImode) + /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */