From patchwork Mon Apr 17 18:20:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 67832 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2526C385558B for ; Mon, 17 Apr 2023 18:21:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id A3F303858C2D for ; Mon, 17 Apr 2023 18:21:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A3F303858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x102e.google.com with SMTP id w11so27134860pjh.5 for ; Mon, 17 Apr 2023 11:21:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681755664; x=1684347664; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:from:to:cc:subject:date :message-id:reply-to; bh=03x6JZnjPYy1dc4t8astsj8H9klrS/s86ZQ+mytF5RY=; b=Pp6NK9jy/ienAUKB6k8u8msYmMdU3rPsuMCXxOVXYLN9TPAdTQy0uC42DHFSQCFeht TkIcqcCu7yNldFnalAIsyBjg3g0ZH4bKBbg6e7PtuzgZKofALVmYSvPbFjV8P8/tQVDk lMf/t3RdYZ3XynQJEpkmTjP4EpL/96FqTjpGbaCf5YR1JU7lwoMtsftxhQRPemo3HdSm Ho/wWzqJV9p8ZxTwJlALsOUm694QJJS/7+1H4O6OFIJQ15WnNb0wgG4fPJbJrYKeZIvh sKGC9kTtHCyB2rYjlDDTVncmS5b7u7mxduW5ZbbQP1WrGjfL8j5IdbXYPNX3nhQQ2fJ6 1/Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681755664; x=1684347664; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=03x6JZnjPYy1dc4t8astsj8H9klrS/s86ZQ+mytF5RY=; b=UFcnOJfDE9TN68kv9iuflNIPZb3Zb10BYhUZsjWb4YnFjwI1dPLr2goREE+pxPk7OF Ibi9x/RoHG14CF2qQs1LsTZVZEcZchlAxKTOBZOyAef4nrA/Yil+bWxQC18e8L0crkvF EoAqzVhoywKVvFXj+RuL/nlyfwoGQMgjaB1EYfCLnNo5dbMAqkOqLA/OhARLNUvICbn/ wbAmMob3EI6858qXg1D1eWN0q6z5psw7NBr3nhzgKsMIKUhQE/h9lYfIKV4b+SqxRvpv ZKBIpys8U6BCnLq/25K/6wHjao1UGQ2eGUeSnl8w8dRFv4pOjxGPQyrVh+sNq2BywXCx pqnA== X-Gm-Message-State: AAQBX9eot+cbPgmRq9Z2BUWc9tbOIb0lsYn49j6lrSLdJsCcgOAFiT5N s67JwZC8TtW3r5+c5U6/T9Q803ZE88RK9sVzqjw= X-Google-Smtp-Source: AKy350Zupy8pyeLDXQOLCH7M15amYDBgN1wFGjjGpyte5FXpbYPDlNnCtktJuUNPsBKBYfkrqaEu/g== X-Received: by 2002:a17:902:e54a:b0:1a2:3b6:8319 with SMTP id n10-20020a170902e54a00b001a203b68319mr16496704plf.54.1681755664372; Mon, 17 Apr 2023 11:21:04 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id q3-20020a170902788300b001a67a37beeesm841137pll.139.2023.04.17.11.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:21:04 -0700 (PDT) Subject: [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase Date: Mon, 17 Apr 2023 11:20:42 -0700 Message-Id: <20230417182044.22425-2-palmer@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230417182044.22425-1-palmer@rivosinc.com> References: <20230417182044.22425-1-palmer@rivosinc.com> MIME-Version: 1.0 Cc: Palmer Dabbelt From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The test case that was added is rv64i-specific, as there's better ways to generate this code on rv32i (where the long/int cast is a NOP) and on rv64i_zba (where we have word shifts). This renames the original test case and adds two more for those targets. gcc/testsuite/ChangeLog: PR target/106602 * gcc.target/riscv/pr106602.c: Moved to... * gcc.target/riscv/pr106602-rv64i.c: ...here. * gcc.target/riscv/pr106602-rv32i.c: New test. * gcc.target/riscv/pr106602-rv64i_zba.c: New test. (cherry picked from commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368) --- gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c | 14 ++++++++++++++ .../riscv/{pr106602.c => pr106602-rv64i.c} | 2 +- .../gcc.target/riscv/pr106602-rv64i_zba.c | 15 +++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c rename gcc/testsuite/gcc.target/riscv/{pr106602.c => pr106602-rv64i.c} (88%) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c new file mode 100644 index 00000000000..05b54db7486 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-O2 -march=rv32i -mabi=ilp32" } */ + +unsigned long +foo2 (unsigned long a) +{ + return (unsigned long)(unsigned int) a << 6; +} + +/* { dg-final { scan-assembler-times "slli\t" 1 } } */ +/* { dg-final { scan-assembler-not "srli\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ +/* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c similarity index 88% rename from gcc/testsuite/gcc.target/riscv/pr106602.c rename to gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c index 825b1a143b5..ef0719f4a9a 100644 --- a/gcc/testsuite/gcc.target/riscv/pr106602.c +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { riscv64*-*-* } } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -march=rv64i -mabi=lp64" } */ unsigned long foo2 (unsigned long a) diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c new file mode 100644 index 00000000000..23b9f1e60f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-O2 -march=rv64i_zba -mabi=lp64" } */ + +unsigned long +foo2 (unsigned long a) +{ + return (unsigned long)(unsigned int) a << 6; +} + +/* { dg-final { scan-assembler-times "slli.uw\t" 1 } } */ +/* { dg-final { scan-assembler-not "slli\t" } } */ +/* { dg-final { scan-assembler-not "srli\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ +/* { dg-final { scan-assembler-not "and\t" } } */