diff mbox series

[13-backport,1/3] RISC-V: Clean up the pr106602.c testcase

Message ID 20230417182044.22425-2-palmer@rivosinc.com
State Committed
Commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368
Headers
Series RISC-V Testsuite Fixes |

Commit Message

Palmer Dabbelt April 17, 2023, 6:20 p.m. UTC 
  The test case that was added is rv64i-specific, as there's better ways
to generate this code on rv32i (where the long/int cast is a NOP) and on
rv64i_zba (where we have word shifts).  This renames the original test
case and adds two more for those targets.

gcc/testsuite/ChangeLog:
	PR target/106602
	* gcc.target/riscv/pr106602.c: Moved to...
	* gcc.target/riscv/pr106602-rv64i.c: ...here.
	* gcc.target/riscv/pr106602-rv32i.c: New test.
	* gcc.target/riscv/pr106602-rv64i_zba.c: New test.

(cherry picked from commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368)
---
 gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c   | 14 ++++++++++++++
 .../riscv/{pr106602.c => pr106602-rv64i.c}        |  2 +-
 .../gcc.target/riscv/pr106602-rv64i_zba.c         | 15 +++++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
 rename gcc/testsuite/gcc.target/riscv/{pr106602.c => pr106602-rv64i.c} (88%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
new file mode 100644
index 00000000000..05b54db7486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv32i -mabi=ilp32" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
similarity index 88%
rename from gcc/testsuite/gcc.target/riscv/pr106602.c
rename to gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
index 825b1a143b5..ef0719f4a9a 100644
--- a/gcc/testsuite/gcc.target/riscv/pr106602.c
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -march=rv64i -mabi=lp64" } */
 
 unsigned long
 foo2 (unsigned long a)
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
new file mode 100644
index 00000000000..23b9f1e60f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv64i_zba -mabi=lp64" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli.uw\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */