From patchwork Fri Apr 7 01:21:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 67477 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA0D13858438 for ; Fri, 7 Apr 2023 01:21:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id DA2623858D32 for ; Fri, 7 Apr 2023 01:21:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA2623858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp73t1680830491t9ybj07a Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 07 Apr 2023 09:21:30 +0800 (CST) X-QQ-SSF: 01400000000000F0O000000A0000000 X-QQ-FEAT: RmDZc/K2LPFpfYwOYFTDqgXvdz/Q3HNXNMiqGDFH9NcMTmFvZASpyOg/Ll+BJ BFKDqd3Lt7BNfUycC/r6/0dkObNiqAgwQcuOriOPasxuPq+S0cYIsWvEDKDqc6nQwgWZzuS C6Ru89HFktZdpJahrqMoJzZldM1KuN5I9Yo1EJag+s+1nvN0rgmc/kLabGCjyBocmcFH4hR XwttsuKWeNmIOIM7QeRWS0Up5t/wC0ygz6dy/myHG7cqZp7cGWGMwpFSfVtC0S60DHg8gbc A0UorbbXUIUTFT/unH1ix4frps43zxGLym8LkI4ndgoSZ6Tpa9NYtAqc89NXfnlDiAsgLMO oBaESnbHn5mGifDwW5nGQJdGB/ZTLf9LEJIZjhe4BGHGxCR/2X9JoRZhNCEybBWpdyVTlD8 X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10647198826086533420 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add RVV auto-vectorization compile option Date: Fri, 7 Apr 2023 09:21:29 +0800 Message-Id: <20230407012129.63142-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong The next patch to enable basic RVV auto-vectorization of VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization (RVV_FIXED_VLMAX). We will support RVV_FIXED_VLMIN in the future. gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add RVV auto-vectorization compile option. (enum riscv_autovec_lmul_enum): Ditto. * config/riscv/riscv.opt: Ditto. --- gcc/config/riscv/riscv-opts.h | 15 ++++++++++++++ gcc/config/riscv/riscv.opt | 37 +++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..4207db240ea 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,21 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RISC-V auto-vectorization preference. */ +enum riscv_autovec_preference_enum { + NO_AUTOVEC, + RVV_SCALABLE, + RVV_FIXED_VLMAX +}; + +/* RISC-V auto-vectorization RVV LMUL. */ +enum riscv_autovec_lmul_enum { + RVV_M1 = 1, + RVV_M2 = 2, + RVV_M4 = 4, + RVV_M8 = 8 +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ff1dd4ddd4f..ef1bdfcfe28 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -254,3 +254,40 @@ Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) misa-spec= Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) Set the version of RISC-V ISA spec. + +Enum +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum) +The RISC-V auto-vectorization preference: + +EnumValue +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC) + +EnumValue +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE) + +EnumValue +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX) + +-param=riscv-autovec-preference= +Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(NO_AUTOVEC) +-param=riscv-autovec-preference= Set the preference of auto-vectorization in the RISC-V port. + +Enum +Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) +The RVV possible LMUL: + +EnumValue +Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1) + +EnumValue +Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2) + +EnumValue +Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4) + +EnumValue +Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8) + +-param=riscv-autovec-lmul= +Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1) +-param=riscv-autovec-lmul= Set the RVV LMUL of auto-vectorization in the RISC-V port.