RISC-V: Add RVV auto-vectorization compile option

Message ID 20230407012129.63142-1-juzhe.zhong@rivai.ai
State Dropped
Headers
Series RISC-V: Add RVV auto-vectorization compile option |

Commit Message

juzhe.zhong@rivai.ai April 7, 2023, 1:21 a.m. UTC
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

The next patch to enable basic RVV auto-vectorization of
VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization (RVV_FIXED_VLMAX).

We will support RVV_FIXED_VLMIN in the future.

gcc/ChangeLog:

        * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add RVV auto-vectorization compile option.
        (enum riscv_autovec_lmul_enum): Ditto.
        * config/riscv/riscv.opt: Ditto.

---
 gcc/config/riscv/riscv-opts.h | 15 ++++++++++++++
 gcc/config/riscv/riscv.opt    | 37 +++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)
  

Comments

Jeff Law April 25, 2023, 6 a.m. UTC | #1
On 4/6/23 19:21, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> The next patch to enable basic RVV auto-vectorization of
> VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization (RVV_FIXED_VLMAX).
> 
> We will support RVV_FIXED_VLMIN in the future.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add RVV auto-vectorization compile option.
>          (enum riscv_autovec_lmul_enum): Ditto.
>          * config/riscv/riscv.opt: Ditto.
No real objection here.  Just a question.   What's the rationale behind 
exposing lmul settings to the user?  I'd think that should largely be 
compiler managed.  But maybe I'm missing something.

jeff
  
juzhe.zhong@rivai.ai April 25, 2023, 6:08 a.m. UTC | #2
Ideally, LMUL should be dynamically picked by compiler according to the user codes.

However, GCC doesn't support it yet and it's not a easy feature to be supported in the future.

My plan is that we let LMUL picked statically according to compile option 
and we fully support and test LMUL = 1/2/4/8 so far.
Then we can support the feature of picking LMUL during auto-vectorization in the future when we figure out how to do that.



juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2023-04-25 14:00
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Add RVV auto-vectorization compile option
 
 
On 4/6/23 19:21, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> The next patch to enable basic RVV auto-vectorization of
> VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization (RVV_FIXED_VLMAX).
> 
> We will support RVV_FIXED_VLMIN in the future.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add RVV auto-vectorization compile option.
>          (enum riscv_autovec_lmul_enum): Ditto.
>          * config/riscv/riscv.opt: Ditto.
No real objection here.  Just a question.   What's the rationale behind 
exposing lmul settings to the user?  I'd think that should largely be 
compiler managed.  But maybe I'm missing something.
 
jeff
  

Patch

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cf0cd669be4..4207db240ea 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,21 @@  enum stack_protector_guard {
   SSP_GLOBAL			/* global canary */
 };
 
+/* RISC-V auto-vectorization preference.  */
+enum riscv_autovec_preference_enum {
+  NO_AUTOVEC,
+  RVV_SCALABLE,
+  RVV_FIXED_VLMAX
+};
+
+/* RISC-V auto-vectorization RVV LMUL.  */
+enum riscv_autovec_lmul_enum {
+  RVV_M1 = 1,
+  RVV_M2 = 2,
+  RVV_M4 = 4,
+  RVV_M8 = 8
+};
+
 #define MASK_ZICSR    (1 << 0)
 #define MASK_ZIFENCEI (1 << 1)
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ff1dd4ddd4f..ef1bdfcfe28 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -254,3 +254,40 @@  Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)
 misa-spec=
 Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
 Set the version of RISC-V ISA spec.
+
+Enum
+Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
+The RISC-V auto-vectorization preference:
+
+EnumValue
+Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
+
+EnumValue
+Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
+
+EnumValue
+Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
+
+-param=riscv-autovec-preference=
+Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(NO_AUTOVEC)
+-param=riscv-autovec-preference=<string>	Set the preference of auto-vectorization in the RISC-V port.
+
+Enum
+Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
+The RVV possible LMUL:
+
+EnumValue
+Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1)
+
+EnumValue
+Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2)
+
+EnumValue
+Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4)
+
+EnumValue
+Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
+
+-param=riscv-autovec-lmul=
+Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1)
+-param=riscv-autovec-lmul=<string>	Set the RVV LMUL of auto-vectorization in the RISC-V port.