From patchwork Thu Apr 6 08:19:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 67447 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C45C9385840F for ; Thu, 6 Apr 2023 08:19:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id D06E13858D39 for ; Thu, 6 Apr 2023 08:19:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D06E13858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.5]) by gateway (Coremail) with SMTP id _____8CxC9qEgC5kwi4XAA--.42067S3; Thu, 06 Apr 2023 16:19:17 +0800 (CST) Received: from 5.5.5 (unknown [10.2.5.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxlryAgC5k8fkWAA--.20128S2; Thu, 06 Apr 2023 16:19:16 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH] LoongArch: Add built-in functions description of LoongArch BASE instruction set instructions. Date: Thu, 6 Apr 2023 16:19:01 +0800 Message-Id: <20230406081900.3588715-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxlryAgC5k8fkWAA--.20128S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoWxur47Ar18AF1UXr43uw1Utrb_yoW5uw1fpw 4Ikry3Ar1rJ347Ww1Syrs5ZFnxXa1vqw1xG39xWr10kF45J3s2qF9IkrWYyrnIyFyruw43 Z348t3yUKa1YkaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b7AYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr 0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1QVy3UUUUU== X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * doc/extend.texi: Add section for LoongArch BASE Built-in functions. --- gcc/doc/extend.texi | 89 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 3adb67aa47a..417af6c368d 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -14669,6 +14669,7 @@ instructions, but allow the compiler to schedule those calls. * Blackfin Built-in Functions:: * BPF Built-in Functions:: * FR-V Built-in Functions:: +* LoongArch BASE Built-in Functions:: * MIPS DSP Built-in Functions:: * MIPS Paired-Single Support:: * MIPS Loongson Built-in Functions:: @@ -16197,6 +16198,94 @@ Use the @code{nldub} instruction to load the contents of address @var{x} into the data cache. The instruction is issued in slot I1@. @end table +@node LoongArch BASE Built-in Functions +@subsection LoongArch BASE Built-in Functions + +These built-in functions are available for LoongArch. + +@itemize +@item @code{imm0_31}, an integer literal in range 0 to 31; +@item @code{imm0_16383}, an integer literal in range 0 to 16383; +@item @code{imm0_32767}, an integer literal in range 0 to 32767; +@item @code{imm_n2048_2047}, an integer literal in range -2048 to 2047; +@item @code{i8, u8, i16, u16, i32, u32, i64, u64, __drdtime_t, __rdtime_t} are included +in @code{larchintrin.h} and defined as follows: +@end itemize + +@smallexample + typedef char i8; + typedef unsigned char u8; + typedef short i16; + typedef unsigned short u16; + typedef int i32; + typedef unsigned int u32; +#if __LONG_MAX__ == __LONG_LONG_MAX__ + typedef long int i64; + typedef unsigned long int u64; +#else + typedef long long i64; + typedef unsigned long long u64; +#endif + + typedef struct drdtime@{ + unsigned long dvalue; + unsigned long dtimeid; + @} __drdtime_t; + + typedef struct rdtime@{ + unsigned int value; + unsigned int timeid; + @} __rdtime_t; +@end smallexample + +The intrinsics provided are listed below; each is named after the +machine instruction. + +@smallexample + __drdtime_t __rdtime_d (void) + __rdtime_t __rdtimel_w (void) + __rdtime_t __rdtimeh_w (void) + u32 __movfcsr2gr (imm0_31) + void __movgr2fcsr (imm0_32, u32) + void __cacop_d (imm0_31, u64, imm_n2048_2047) + u32 __cpucfg (u32) + void __asrtle_d (i64, i64) + void __asrtgt_d (i64, i64) + i64 __lddir_d (i64, imm0_31) + void __ldpte_d (i64, imm0_31) + + i32 __crc_w_b_w (i8, i32) + i32 __crc_w_h_w (i16, i32) + i32 __crc_w_w_w (i32, i32) + i32 __crc_w_d_w (i64, i32) + i32 __crcc_w_b_w (i8, i32) + i32 __crcc_w_h_w (i16, i32) + i32 __crcc_w_w_w (i32, i32) + i32 __crcc_w_d_w (i64, i32) + + u32 __csrrd_w (imm0_16383) + u32 __csrwr_w (u32, imm0_16383) + u32 __csrxchg_w (u32, u32, imm0_16383) + u64 __csrrd_d (imm0_16383) + u64 __csrwr_d (u64, imm0_16383) + u64 __csrxchg_d (u64, u64, imm0_16383) + + u8 __iocsrrd_b (u32) + u16 __iocsrrd_h (u32) + u32 __iocsrrd_w (u32) + u64 __iocsrrd_d (u32) + void __iocsrwr_b (u8, u32) + void __iocsrwr_h (u16, u32) + void __iocsrwr_w (u32, u32) + void __iocsrwr_d (u64, u32) + + void __dbar (imm0_32767) + void __ibar (imm0_32767) + + void __syscall (imm0_32767) + void __break (imm0_32767) +@end smallexample + @node MIPS DSP Built-in Functions @subsection MIPS DSP Built-in Functions