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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id jw20-20020a170903279400b001a0428bd8c4sm21175788plb.289.2023.03.28.07.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 07:27:01 -0700 (PDT) To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com Cc: Kito Cheng Subject: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312] Date: Tue, 28 Mar 2023 22:26:57 +0800 Message-Id: <20230328142657.53724-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Gcc-patches From: Kito Cheng Reply-To: Kito Cheng Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" RVV intrinsic has defined a macro to identity the version of RVV intrinsic spec, we missed that before, thanksful we are catch this before release. gcc/ChangeLog: PR target/109312 * config/riscv/riscv-c.cc (riscv_ext_version_value): New. (riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and minor refactor. gcc/testsuite/ChangeLog: PR target/109312 * gcc.target/riscv/predef-__riscv_v_intrinsic.c: New test. --- gcc/config/riscv/riscv-c.cc | 18 ++++++++++++++---- .../riscv/predef-__riscv_v_intrinsic.c | 11 +++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index ff07d319d0b..6ad562dcb8b 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -34,6 +34,12 @@ along with GCC; see the file COPYING3. If not see #define builtin_define(TXT) cpp_define (pfile, TXT) +static int +riscv_ext_version_value (unsigned major, unsigned minor) +{ + return (major * 1000000) + (minor * 1000); +} + /* Implement TARGET_CPU_CPP_BUILTINS. */ void @@ -118,7 +124,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define_with_int_value ("__riscv_v_elen_fp", 0); if (TARGET_MIN_VLEN) - builtin_define ("__riscv_vector"); + { + builtin_define ("__riscv_vector"); + builtin_define_with_int_value ("__riscv_v_intrinsic", + riscv_ext_version_value (0, 11)); + } /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1); @@ -141,13 +151,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) subset != subset_list->end (); subset = subset->next) { - int version_value = (subset->major_version * 1000000) - + (subset->minor_version * 1000); + int version_value = riscv_ext_version_value (subset->major_version, + subset->minor_version); /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or earlier. */ if ((subset->name == "zicsr" || subset->name == "zifencei") && version_value == 0) - version_value = 2000000; + version_value = riscv_ext_version_value (2, 0); sprintf (buf, "__riscv_%s", subset->name.c_str ()); builtin_define_with_int_value (buf, version_value); diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c new file mode 100644 index 00000000000..dbbedf54f87 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imafdcv -mabi=lp64d" } */ + +int main () { + +#if __riscv_v_intrinsic != 11000 +#error "__riscv_v_intrinsic" +#endif + + return 0; +}