diff mbox series

RISC-V: Define __riscv_v_intrinsic [PR109312]

Message ID 20230328142657.53724-1-kito.cheng@sifive.com
State Committed
Commit 5a923516ae61ddc6dd863891db13189cbf392411
Headers
Series RISC-V: Define __riscv_v_intrinsic [PR109312] |

Commit Message

Kito Cheng March 28, 2023, 2:26 p.m. UTC 
  RVV intrinsic has defined a macro to identity the version of RVV
intrinsic spec, we missed that before, thanksful we are catch this
before release.

gcc/ChangeLog:

	PR target/109312
	* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
	(riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
	minor refactor.

gcc/testsuite/ChangeLog:

	PR target/109312
	* gcc.target/riscv/predef-__riscv_v_intrinsic.c: New test.
---
 gcc/config/riscv/riscv-c.cc                    | 18 ++++++++++++++----
 .../riscv/predef-__riscv_v_intrinsic.c         | 11 +++++++++++
 2 files changed, 25 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c

Comments

钟居哲 March 28, 2023, 2:33 p.m. UTC | #1 
LGTM。



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-03-28 22:26
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong; jeffreyalaw
CC: Kito Cheng
Subject: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312]
RVV intrinsic has defined a macro to identity the version of RVV
intrinsic spec, we missed that before, thanksful we are catch this
before release.
 
gcc/ChangeLog:
 
PR target/109312
* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
(riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
minor refactor.
 
gcc/testsuite/ChangeLog:
 
PR target/109312
* gcc.target/riscv/predef-__riscv_v_intrinsic.c: New test.
---
gcc/config/riscv/riscv-c.cc                    | 18 ++++++++++++++----
.../riscv/predef-__riscv_v_intrinsic.c         | 11 +++++++++++
2 files changed, 25 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ff07d319d0b..6ad562dcb8b 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -34,6 +34,12 @@ along with GCC; see the file COPYING3.  If not see
#define builtin_define(TXT) cpp_define (pfile, TXT)
+static int
+riscv_ext_version_value (unsigned major, unsigned minor)
+{
+  return (major * 1000000) + (minor * 1000);
+}
+
/* Implement TARGET_CPU_CPP_BUILTINS.  */
void
@@ -118,7 +124,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
     builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
   if (TARGET_MIN_VLEN)
-    builtin_define ("__riscv_vector");
+    {
+      builtin_define ("__riscv_vector");
+      builtin_define_with_int_value ("__riscv_v_intrinsic",
+      riscv_ext_version_value (0, 11));
+    }
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
@@ -141,13 +151,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
        subset != subset_list->end ();
        subset = subset->next)
     {
-      int version_value = (subset->major_version * 1000000)
-    + (subset->minor_version * 1000);
+      int version_value = riscv_ext_version_value (subset->major_version,
+    subset->minor_version);
       /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or
earlier.  */
       if ((subset->name == "zicsr" || subset->name == "zifencei")
  && version_value == 0)
- version_value = 2000000;
+ version_value = riscv_ext_version_value (2, 0);
       sprintf (buf, "__riscv_%s", subset->name.c_str ());
       builtin_define_with_int_value (buf, version_value);
diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
new file mode 100644
index 00000000000..dbbedf54f87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcv -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_v_intrinsic != 11000
+#error "__riscv_v_intrinsic"
+#endif
+
+  return 0;
+}
-- 
2.39.2
Kito Cheng March 28, 2023, 3:22 p.m. UTC | #2 
Applied to trunk :)

<juzhe.zhong@rivai.ai>於 2023年3月28日 週二，22:34寫道：

> LGTM。
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Kito Cheng
> Date: 2023-03-28 22:26
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong;
> jeffreyalaw
> CC: Kito Cheng
> Subject: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312]
> RVV intrinsic has defined a macro to identity the version of RVV
> intrinsic spec, we missed that before, thanksful we are catch this
> before release.
>
> gcc/ChangeLog:
>
> PR target/109312
> * config/riscv/riscv-c.cc (riscv_ext_version_value): New.
> (riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
> minor refactor.
>
> gcc/testsuite/ChangeLog:
>
> PR target/109312
> * gcc.target/riscv/predef-__riscv_v_intrinsic.c: New test.
> ---
> gcc/config/riscv/riscv-c.cc                    | 18 ++++++++++++++----
> .../riscv/predef-__riscv_v_intrinsic.c         | 11 +++++++++++
> 2 files changed, 25 insertions(+), 4 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index ff07d319d0b..6ad562dcb8b 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -34,6 +34,12 @@ along with GCC; see the file COPYING3.  If not see
> #define builtin_define(TXT) cpp_define (pfile, TXT)
> +static int
> +riscv_ext_version_value (unsigned major, unsigned minor)
> +{
> +  return (major * 1000000) + (minor * 1000);
> +}
> +
> /* Implement TARGET_CPU_CPP_BUILTINS.  */
> void
> @@ -118,7 +124,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>      builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
>    if (TARGET_MIN_VLEN)
> -    builtin_define ("__riscv_vector");
> +    {
> +      builtin_define ("__riscv_vector");
> +      builtin_define_with_int_value ("__riscv_v_intrinsic",
> +      riscv_ext_version_value (0, 11));
> +    }
>    /* Define architecture extension test macros.  */
>    builtin_define_with_int_value ("__riscv_arch_test", 1);
> @@ -141,13 +151,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>         subset != subset_list->end ();
>         subset = subset->next)
>      {
> -      int version_value = (subset->major_version * 1000000)
> -    + (subset->minor_version * 1000);
> +      int version_value = riscv_ext_version_value (subset->major_version,
> +    subset->minor_version);
>        /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2
> or
> earlier.  */
>        if ((subset->name == "zicsr" || subset->name == "zifencei")
>   && version_value == 0)
> - version_value = 2000000;
> + version_value = riscv_ext_version_value (2, 0);
>        sprintf (buf, "__riscv_%s", subset->name.c_str ());
>        builtin_define_with_int_value (buf, version_value);
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> new file mode 100644
> index 00000000000..dbbedf54f87
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64imafdcv -mabi=lp64d" } */
> +
> +int main () {
> +
> +#if __riscv_v_intrinsic != 11000
> +#error "__riscv_v_intrinsic"
> +#endif
> +
> +  return 0;
> +}
> --
> 2.39.2
>
>
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ff07d319d0b..6ad562dcb8b 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -34,6 +34,12 @@  along with GCC; see the file COPYING3.  If not see
 
 #define builtin_define(TXT) cpp_define (pfile, TXT)
 
+static int
+riscv_ext_version_value (unsigned major, unsigned minor)
+{
+  return (major * 1000000) + (minor * 1000);
+}
+
 /* Implement TARGET_CPU_CPP_BUILTINS.  */
 
 void
@@ -118,7 +124,11 @@  riscv_cpu_cpp_builtins (cpp_reader *pfile)
     builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
 
   if (TARGET_MIN_VLEN)
-    builtin_define ("__riscv_vector");
+    {
+      builtin_define ("__riscv_vector");
+      builtin_define_with_int_value ("__riscv_v_intrinsic",
+				     riscv_ext_version_value (0, 11));
+    }
 
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
@@ -141,13 +151,13 @@  riscv_cpu_cpp_builtins (cpp_reader *pfile)
        subset != subset_list->end ();
        subset = subset->next)
     {
-      int version_value = (subset->major_version * 1000000)
-			   + (subset->minor_version * 1000);
+      int version_value = riscv_ext_version_value (subset->major_version,
+						   subset->minor_version);
       /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or
 	 earlier.  */
       if ((subset->name == "zicsr" || subset->name == "zifencei")
 	  && version_value == 0)
-	version_value = 2000000;
+	version_value = riscv_ext_version_value (2, 0);
 
       sprintf (buf, "__riscv_%s", subset->name.c_str ());
       builtin_define_with_int_value (buf, version_value);
diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
new file mode 100644
index 00000000000..dbbedf54f87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcv -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_v_intrinsic != 11000
+#error "__riscv_v_intrinsic"
+#endif
+
+  return 0;
+}